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Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
To develop Arm Cortex-M0 based SoCs, from creating high-level functional specifications to design, implementation and testing on FPGA platforms using standard hardware description and software prog…
This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit
Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was verified using QuestaSim.
All labs for this class are located here. This repository is intended for potential employers to look at to verify knowledge of SoC Design with FPGA..
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
The basic code for transmitting and recieving data.
My personally created drivers for some peripherals of STM32
Contains the code examples from The UVM Primer Book sorted by chapters.
A collection of C solutions for various Leetcode problems.
A curated list of awesome C++ (or C) frameworks, libraries, resources, and shiny things. Inspired by awesome-... stuff.
A curated list of awesome C frameworks, libraries, resources and other shiny things. Inspired by all the other awesome-... projects out there.
Mastering Embedded Linux Programming – Second Edition, published by Packt
Mastering Embedded Linux Programming Third Edition, published by Packt
Companion repository to the "Modern Embedded Systems Programming" video course.
A curated list of awesome embedded programming.
Research and Materials on Hardware implementation of Transformer Model
System Verilog for ASIC/FPGA Design & Simulation 2023 is an online course conducted by ENTC. This repository contains all the source files that I created during the course
UCSB ECE594BB Instructed by Prof. Peng Li in Winter 2023
Master the command line, in one page
How to write a UNIX shell, with a lot of background
Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
MIPS and uPower Datapath for CS250 - Computer Organisation and Architecture Lab @ NIT-Surathkal
DDR SDRAM Controller based on Xilinx MIG for Digilent Boards