nano-cpu32k is a high-performance RISC processor core.
| Feature | nano-cpu32k |
|---|---|
| Superscalar | √ |
| Out-of-order issue/execution | √ |
| Boot Linux | √ |
| L1 Cache & MMU | √ |
| AXI4 Memory interface | √ |
| Instruction fetch width | 4 (Configurable) |
| Issue width | 2 (Configurable) |
| Dynamic branch prediction | √ |
| Synthesizable Verilog | √ |
| FPGA Verified | √ |
| Clock frequency on FPGA | >100MHz @Kintex-7 |
The micro-architecture overview is shown below.
- Install
python3. - Run
make buildto generate the Verilog filebuild/ysyx_210479.v
- Install Verilog simulator
Verilator. - Run
make build_simto generate the simulation programbuild/emu. - Run
build/emu --helpfor a overview of supported options.
Run the prebuilt Linux:
./build/emu --mode=standalone -b ./prebuilt/vmlinux.bin --flash-image=./prebuilt/bsp/program/flash/trampoline-flash.bin --reset-pc=0x30000000Alternatively, using the --mode=difftest option, you can do differential test between hardware implementation and C++ reference model.
- Run
run-test.shto test hardware design.
A DDR3-based minimum SoC is provided on fpga\ddr3_alpha_soc in the form of Vivado project.
- See
fpga\ddr3_alpha_soc\PINs.xlsxfor hardware connections. - Program SPI flash with binary file
prebuilt\bsp\program\loader\vmlinux-loader.binstarting at address 0x0. - Connect the RS232 serial port to your PC, set baud rate as 115200 bps.
- Download the bitstream to FPGA.