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naavaneetha / Project-Based-Experiment
YosysHQ / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
avmwww / sdio-audio
SDIO Audio device. Verilog.
OSCPU / yosys-sta
RESMIRNAIR / SR_FLIPFLOP
ufrisk / pcileech-fpga
FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
Misaka-N / TJCS-SingleCircleCPU31
同济大学2021级计算机科学与技术系 计算机组成与原理实验 单周期31条指令CPU
OSCPU / ysyxSoC
lnis-uofu / OpenFPGA
An Open-source FPGA IP Generator
alexforencich / verilog-axi
Verilog AXI components for FPGA implementation
RESMIRNAIR / MEALY_1101
RESMIRNAIR / MOORE_1011
The-OpenROAD-Project / OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
efabless / caravel_user_project
phoeniX-Digital-Design / phoeniX
phoeniX RISC-V Processor