adam-maj / tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
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A minimal GPU design in Verilog to learn how GPUs work from the ground up
OpenTitan: Open source silicon root of trust
RISC-V Debug Support for our PULP RISC-V Cores
[UNRELEASED] FP div/sqrt unit for transprecision
NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards
Generic Register Interface (contains various adapters)
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Common SystemVerilog components
SystemVerilog modules and classes commonly used for verification
AXI Adapter(s) for RISC-V Atomic Operations
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6