ucb-bar / nvdla-wrapper
Wraps the NVDLA project for Chipyard integration
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Wraps the NVDLA project for Chipyard integration
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Verilog Ethernet components for FPGA implementation
PicoRV32 - A Size-Optimized RISC-V CPU
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/