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vivado

Here are 556 public repositories matching this topic...

Logicademy / PYNQ-SoC-Builder

This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.

python automation fpga vhdl verilog xilinx vivado hardware-designs hdl hdlgen-chatgpt

Updated Sep 11, 2024
Python

ichi4096 / vivado-on-silicon-mac

Installs Vivado on M1/M2 macs

macos docker arm fpga vivado arm64 aarch64 vivado-installer

Updated Sep 11, 2024
C

hls4ml

fastmachinelearning / hls4ml

Machine learning on FPGAs using HLS

python machine-learning fpga neural-network hls keras pytorch vivado vivado-hls onnx intel-hls

Updated Sep 11, 2024
C++

RDSik / i2c-master

python fpga chocolatey verilog make vivado icarus-verilog modelsim quartus winget cocotb hdlmake

Updated Sep 11, 2024
Verilog

RDSik / verilog-transceiver

Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

python fpga chocolatey verilog make vivado icarus-verilog modelsim winget cocotb hdlmake

Updated Sep 10, 2024
Verilog

mwrnd / notes

Various Notes and Tutorials

vivado ddr4 xdma xdma-stream

Updated Sep 9, 2024
Tcl

mwrnd / innova2_flex_xcku15p_notes

Nvidia/Mellanox Innova-2 Flex Open Programmable SmartNIC Setup and Usage Notes for XCKU15P FPGA Development

fpga vivado urjtag kintex-ultrascale innova2 xcku15p mt27808a0 mt28808a0 mnv303212a innova-2-flex mnv303212a-adlt mnv303611a-edlt 4xc7a16683 01pg974 nv303212a innova2-8gb-adlt

Updated Sep 8, 2024
Tcl

PyFPGA / pyfpga

A Python package to use FPGA development tools programmatically.

python fpga amd tcl intel trellis xilinx vivado altera ise icestorm lattice microchip ghdl yosys quartus microsemi nextpnr actel libero

Updated Sep 8, 2024
Python

MohamedHussein27 / RISC-V-Single-Cycle-Implementation

This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book. The project includes a complete Verilog implementation, supporting various instruction types, with performance enhancements and detailed schematics for analysis.

vivado computer-architecture digital-design quartus-prime verilog-project rtl-design

Updated Sep 6, 2024
Verilog

Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado

fpga xilinx vivado rapidwright

Updated Sep 12, 2024
Java

hdl-modules

hdl-modules / hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

asic fpga hardware amd vhdl intel eda rtl ip xilinx vivado altera fifo cdc axi microsemi clock-domain-crossing asynchronous-fifo axi-lite efinix

Updated Sep 6, 2024
VHDL

mshr-h / vscode-verilog-hdl-support

HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Sep 10, 2024
TypeScript

junwha0511 / MNIST-FPGA-Accelarator

MNIST accelerator using pynq-z2 and the binary qunatization

mnist mnist-classification vivado pynq hardware-acceleration mnist-image-dataset vivado-hls pynq-z2

Updated Sep 4, 2024
C++

AlvaroDavi5 / Programacao_e_Desenvolvimento

vhdl vscode cad xilinx vivado ise qucs qcad eagle-pcb

Updated Sep 4, 2024
JavaScript

jorgeiglesiasc / advanced-rfsoc-front-end

Advanced multi-band GNSS SDR front-end implementation in an RFSoC integrated circuit. GPL-3.0 license

python c-plus-plus front-end signal-processing sdr vivado gnss rfsoc vitis-hls multi-band direct-rf-sampling

Updated Sep 3, 2024
Jupyter Notebook

barrettotte / fpga-dev-vscode

Simple FPGA development workflow with VS Code

fpga vscode vivado

Updated Sep 3, 2024
Tcl

pavel-demin / red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

radio linux fpga zynq dsp tcl verilog nmr xilinx sdr mca redpitaya vna vivado wspr red-pitaya vitis

Updated Sep 2, 2024
Tcl

SUHANI102003 / VERILOG-SEQUENTIAL_CIRCUITS

Verilog codes for sequential circuits

simulation vivado counters testbench verilog-hdl registers digital-electronics flip-flops latches

Updated Sep 1, 2024
Verilog

Teddy-van-Jerry / vitis-hls-examples

Vitis (Vivado) HLS Examples

hls cpp cpp14 vivado high-level-synthesis vivado-hls vitis vitis-hls

Updated Sep 1, 2024
C++

yasnakateb / VectorOps

🏄 Custom IP for vector operations

zynq vector vhdl vivado hardware-designs hdl custom-ip fpga-accelerator axi vitis axi-lite vector-operation vector-ops vector-operations

Updated Aug 31, 2024
VHDL

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