This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
-
Updated
Sep 11, 2024 - Python
This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
Machine learning on FPGAs using HLS
Nvidia/Mellanox Innova-2 Flex Open Programmable SmartNIC Setup and Usage Notes for XCKU15P FPGA Development
This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book. The project includes a complete Verilog implementation, supporting various instruction types, with performance enhancements and detailed schematics for analysis.
Build Customized FPGA Implementations for Vivado
HDL support for VS Code
MNIST accelerator using pynq-z2 and the binary qunatization
Advanced multi-band GNSS SDR front-end implementation in an RFSoC integrated circuit. GPL-3.0 license
Verilog codes for sequential circuits
Vitis (Vivado) HLS Examples
🏄 Custom IP for vector operations
Add a description, image, and links to the vivado topic page so that developers can more easily learn about it.
To associate your repository with the vivado topic, visit your repo's landing page and select "manage topics."