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vhdl-code

Here are 268 public repositories matching this topic...

stevsvc / Energy_Monitor

fpga-board vhdl-code

Updated Mar 17, 2018
VHDL

HuzaifaElahi / Space-Invaders

Updated Aug 29, 2018
VHDL

12BIT-Counter-to-7segment-output-VHDL-FPGA

MohammadNiknam17 / 12BIT-Counter-to-7segment-output-VHDL-FPGA

These are VHDL codes for 12Bit counter to 7segment output. contains binary to BCD converter base on double dabble algorithm.

counter fpga binary vhdl double-dabble-algorithm bcd 7segment vhdl-code

Updated May 28, 2021
VHDL

touunix / Simple-stopwatch-VHDL

Simple stopwatch VHDL | Prosty stoper VHDL

fpga simulation stopwatch vhdl vhdl-code simple-stopwatch

Updated Mar 27, 2022
VHDL

charrat0649 / BE_VHDL_M2SME_Binome3

L’objectif de ce bureau d’étude est de concevoir le pilote de barre franche sous forme d’un système sur puce programmable SOPC (System On Programmable Chip) décrite à l’aide du langage de description de Hardware VHDL (Very High Speed Hardware Description Langage) en se basant sur l’analyse de spécifications et découpage fonctionnel du système ch…

Updated Dec 14, 2021
C

onegentig / VUT-FIT-INP2022-projekt1

První projekt (CPU s brainfuck-like ISA) z předmětu Návrh počítačových systémů (INP), třetí semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023

processor-architecture microcontroller cpu fpga vhdl brainfuck university-project isa vutbr vut inp cpu-simulator vhdl-code cpu-architecture vut-fit brainlove vhdl-coursework brno-university-of-technology

Updated Jan 13, 2024
VHDL

Erfangholiz / My-VHDL

A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.

vhdl verilog logic-gates modelsim verilog-hdl logic-circuit logical-gates quartus vhdl-code logical-circuits vhdl-examples verilog-project quartus2 verilog-code

Updated May 24, 2024
Verilog

talisma-cassoma / finite-state-machine-FSM

Moore and Mealy Machine architecture (model)

state-machine moore-machine vhdl-code

Updated Mar 15, 2022
VHDL

aliansgp / VHDL_Adders

Different adders code in VHDL and Comparison

vhdl vhd computer-architecture adder computer-architecture-lesson half-adder vhdl-code adders vhdl-examples full-adder ripple-adder look-ahead-adder carry-save-adder

Updated Feb 7, 2023
C

b57zheng / FPGA_HVAC

Control program for Heating, Ventilation, Air-conditioning and Cooling unit.

fpga vhdl-code hvac-control

Updated Apr 15, 2023
VHDL

DericAugusto / ISN2023_DigitalSystems

Material from the course of Design of Digital Systems at ENSEM - Université de Lorraine.

boolean-algebra quartus boolean-logic vhdl-code fpga-programming combinatorial-logic dynamic-modeling

Updated Sep 17, 2023
VHDL

SamsonAdem / HW_SW_Co_Design_FPGA

Hardware accelerator for Image processing in FPGA

cpp hardware vhdl image-processing xilinx-fpga median-filter vhdl-code hardwareaccelerator vitis-hls

Updated Oct 3, 2023
C++

farbodfld / CoDesign-Course

Projects of CoDesign course at SBU

vhdl codesign vhdl-modules vhdl-code

Updated Aug 14, 2023
VHDL

Tanmaymundra / vhdl

This repository contains example of logic such as comparator, encoder, etc in vhdl. Feel Free to add other examples in this repository

vhdl vhdl-code vhdl-examples

Updated Dec 17, 2019
VHDL

onegentig / VUT-FIT-INC2022-projekt

Projekt (UART přijímací část) z předmětu Návrh číslicových systémů (INC), druhý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2021/2022

fsm fpga vhdl university-project xilinx uart xilinx-fpga vutbr vut vhdl-code vut-fit vhdl-coursework uart-receiver brno-university-of-technology

Updated Jan 12, 2024
VHDL

Man2Dev / Computer-Design-of-Digital-Systems-course

Some of my CAD projects

university vhdl university-project cad university-course computer-aided-design university-assignment vhdl-code activehdl

Updated Dec 24, 2023
VHDL

CodiieSB / VHDL-4x1MUX

The VHDL code implements a 4x1 multiplexer (MUX), selecting one of four input signals based on the two select lines and producing a single output.

vhdl xilinx-vivado 4x1mux vhdl-code

Updated Feb 28, 2024
VHDL

CodiieSB / VHDL-2x4Decoder

The VHDL code implements a 2x4 decoder, converting two input signals into four output signals based on the input combinations.

vhdl xilinx-vivado vhdl-code vhdl-examples 2x4-decoder

Updated Feb 28, 2024
VHDL

esch3r / Microfluidics

References and supplemental material for for projects involving programming of a microfluidics array

microfluidics vhdl-code vhdl-examples verilog-project puddle

Updated Nov 25, 2019
SystemVerilog

pankajpatro703 / hdlang-ex

Hardware Description Language(HDL) based codes using Verilog & VHDL for reference.

hdl vhdl-code verilog-code

Updated Sep 15, 2020
Verilog

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