Example designs showing different ways to use F4PGA toolchains.

FPGA tool performance profiling

FPGA Assembly (FASM) Parser and Generator

Plugins for Yosys developed as part of the F4PGA project.

Python interface to FPGA interchange format

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

Repository to run extensive tests on the FPGA interchange format

Open source flow for generating bitstreams from Chisel code