Stars
A complete open-source design-for-testing (DFT) Solution
This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
VSD Workshop on RTL Design using Verilog HDL and Synthesis with Optimization using SKY130 Technology
A list of resources related to the open-source FPGA projects
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
A collection of Master XDC files for Digilent FPGA and Zynq boards.
Its a workshop conducted by VSD team
An Open-Source Design and Verification Environment for RISC-V
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
Free Introduction to Bash Scripting eBook
Curated resources help you prepare for the CNCF/Linux Foundation CKS 2021 "Kubernetes Certified Security Specialist" Certification exam. Please provide feedback or requests by raising issues, or ma…
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room tempe…
A collection of data science and machine learning resources that I've found helpful (I only post what I've read!)
High Level Synthesis FPGA example of QAM demodulator using Vivado HLS
AXI Formal Verification IP
this repo contains hdl codes for digital circuits.
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment