I'm Shubham Pandey. I do digital and system design usign hdl. I really enjoy learning synthesizable constructs and FPGA as well. I am also exploring hardware for Computational Neuroscience.

Skills: Verilog/ C++

• 🔭 I’m currently working on Systolic Processor array and data acquisition system.
• 💻 I'm currently learning system verilog for design and c++.
• 🌱 I’m trying projects on FPGA board and understanding FPGA architecture.
• 👯 I’m looking to collaborate on Projects related to FPGA design.
• 🤔 I’m looking for help with mapping and translation of design into FPGA i.e. backend stuff realated to FPGA synthesis.
• 💬 Ask me about Digital Design, RTL design, FPGA, Hardware Accelerators, Computational Neuroscience.
• 📝 I have also designed synthesizable AMBA protocol based AHB APB bus bridge and slave peripheral.
• 📫 How to reach me: [email protected]
• 😄 Pronouns: SpeedyPandey
• ⚡ Fun fact: you learn more when you try!