Stars
A handy way to parse, store and access JSON data from files or strings in LaTeX documents
Python-based Hardware Design Processing Toolkit for Verilog HDL
An antidote to remove wildcard I/O instantiations from Verilog and SystemVerilog files.
A simple superscalar out-of-order RISC-V microprocessor
CoreFreq : CPU monitoring and tuning software designed for 64-bit processors.
Multilevel TLB implementation workspace for (CVA6) Ariane Core during summer GSoC'21
Open-source high-performance RISC-V processor
cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
RISC-V Functional ISA Simulator
A pandoc LaTeX template to convert markdown files to PDF or LaTeX.
An implementation of WaveDrom which outputs TikZ for use in LaTeX documents.
Rune is a programming language developed to test ideas for improving security and efficiency.
A Chisel RTL generator for network-on-chip interconnects
RSD: RISC-V Out-of-Order Superscalar Processor
Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python
Guide on how to use Qemu to create a similar effect to Windows Subsystem for Linux on macOS. Unfinished; contributions are welcome!
An open-source static random access memory (SRAM) compiler.
🌈 Simpler Rainbow Parentheses