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UC Irvine
- Irvine, CA
- https://www.linkedin.com/in/ranjithdhananjaya
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A 2 stage CMOS OTA with Differential amplifier with active load as the first stage followed by Common Source stage using Cadence
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Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process
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This repository contains the .cst files and results of simulation of the antenna project.
1 UpdatedFeb 12, 2022 -
Step Response of RC Low Pass & High Pass Filters
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This repository contains the files used in the design and simulation of Indian Regional Navigation Satellite System (IRNSS) Signal Generator
UpdatedJan 3, 2022 -
This repository contains the files of my undergrad Major project.
engineering machine-learning deep-neural-networks neural-network image-processing python3 convolutional-neural-network4 UpdatedJan 3, 2022 -
Cadence-lab-simulations Public
This repository contains the files (schematic, test bench, simulation results) from the course Mixed-Signal Design(undergrad)
2 UpdatedJan 3, 2022 -
Design of inverter layout using Magic VLSI Layout opensource EDA tool and NgSpice
1 UpdatedDec 22, 2021 -
This repository contains the files used in the project - "automatic licence plate recognition"