-
Siemens EDA
- Netherlands
- https://www.linkedin.com/in/rafaelcalcada/
Block or Report
Block or report rafaelcalcada
Contact GitHub support about this user’s behavior. Learn more about reporting abuse.
Report abuseLists (1)
Sort Name ascending (A-Z)
Stars
Language
Sort by: Recently starred
Test suite designed to check compliance with the SystemVerilog standard.
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
A Python Library for Data Models Persisted in Redis
Free collection of hardware modules written in Verilog for FPGAs and embedded systems.
A collection of image processing and computer vision algorithms in C++17 using Boost.GIL and Blaze linear algebra library
Architectural Tests for RISC-V Steel Processor Core IP
The Fast Lexical Analyzer - scanner generator for lexing in C and C++
Yet Another Syntax Highlighter for lex/yacc & flex/bison.
An AXI4 crossbar implementation in SystemVerilog
Implementing a RISC-V CPU on FPGA(Cyclone II)
Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, documentation, and sample programs. Completed as part of our…
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
Converts ELF files to HEX files that are suitable for Verilog's readmemh.
A digital logic designer and circuit simulator.
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
A beautiful stack trace pretty printer for C++
GNU toolchain for RISC-V, including GCC
kantooon / gr-dsss
Forked from ericdegroot/gr-dsssGNU radio Direct Sequence Spread Spectrum blocks
Showcase examples for EPFL logic synthesis libraries