Stars
Source code & scripts for distributed machine learning training workloads on a real-world Processing-In-Memory system (i.e., UPMEM). Described in our PACT'24 paper by Rhyner et al. at https://arxiv…
A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arxiv.org/pdf/2406.18786
Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input majority operations and 3) copying one row's content to up 31 r…
Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used i…
Source code for the architectural simulator used for modeling the PUD system proposed in our HPCA 2024 paper `MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficie…
Source code & scripts for experimental characterization and demonstration of performing NOT and up to 16-input AND, NAND, OR, and NOR operations in real DDR4 DRAM chips. Described in our HPCA'24 pa…
RUBICON is a novel framework to automatically develop deep-learning-based genomic basecallers for any given architecture, as described in our Genome Biology'24 paper https://genomebiology.biomedc
MetaTrinity is a novel metagenomic analysis tool employing efficient containment search techniques and heuristics for read mapping to achieve significant speedup while maintaining high accuracy. Th…
CoMeT is a new low-cost RowHammer mitigation that uses Count-Min Sketch-based aggressor row tracking, as described in our HPCA'24 paper https://arxiv.org/pdf/2402.18769.pdf
Virtuoso is a new simulator that focuses on modelling various memory management and virtual memory aspects.
SequenceLab is a benchmark suite for evaluating computational methods for comparing genomic sequences, such as pre-alignment filters and pairwise sequence alignment algorithms. SequenceLab is descr…
SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 2023 paper by Chen et al. (https://arxiv.org/pdf/2310.01893.pdf).
New RowHammer mitigation mechanism that is area-, performance-, and energy-efficient especially at very low (e.g., 125) RowHammer thresholds, as described in the USENIX Security'24 paper https://ar…
RawAlign is a real-time raw nanopore read mapper based on the Seed-Filter-Align paradigm as described by Lindegger et al. (https://arxiv.org/abs/2310.05037)
Utopia is a new hybrid address mapping scheme that accelerates address translation while supporting all conventional VM features as described by Kanellopoulos et al. (https://arxiv.org/abs/2211.12205)
GateSeeder is the first near-memory CPU-FPGA co-design for alleviating both the compute-bound and memory-bound bottlenecks in short and long-read mapping. GateSeeder outperforms Minimap2 by up to 4…
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM stan…
Victima is a new software-transparent technique that greatly extends the address translation reach of modern processors by leveraging the underutilized resources of the cache hierarchy, as desribed…
An extensible and fully programable cycle-accurate Spatial Architecture simulator for Machine Learning Workloads. Described in detail in the IEEE TC 2023 paper by Orosa et al. at https://arxiv.org/…
Experimental study and analysis on the effect of using a wide range of different supply voltage values on the reliability, latency, and retention characteristics of DDR3L DRAM SO-DIMMs
CMU-SAFARI / ThyNVM
Forked from basicthinker/ThyNVMThyNVM: Transparent hybrid NonVolatile Memory. A gem5-based persistent memory simulator that implements a DRAM+NVM hybrid memory architecture. Introduced in the MICRO 2015 paper: https://users.ece.…
A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
A cycle-accurate simulator that models a hybrid memory subsystem consisting of multiple memory technologies. Described in the CLUSTER 2017 paper by Li et al. (https://people.inf.ethz.ch/omutlu/pub/…
LTRF's register-interval creation algorithm divides the control flow graph (CFG) of a GPU application into some register-intervals which have two main characteristics: 1) register-intervals have on…
Latency characterization data collected from 30 real DRAM SO-DIMMs. You can find the background and analysis on the data in our SIGMETRICS'16 paper "Understanding Latency Variation in Modern DRAM C…
This simulator models Simultaneous Multi Layer Access (SMLA) and 3D-stacked DRAM memory, based on the TACO 2016 paper https://users.ece.cmu.edu/~omutlu/pub/smla_high-bandwidth-3d-stacked-memory_tac…
This is a patch on GPGPU-sim for MeDiC. MeDiC is a mechanism that reduces the negative performance impact of memory divergence and cache queuing in GPUs. It is introduced in the PACT 2015 paper by …