本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。

Naive Educational RISC V processor

毛泽东选集

Altera Advanced Synthesis Cookbook 11.0

VeeR EL2 Core

SERV - The SErial RISC-V CPU

Verilog module for flexible instantiation of ROM/RAM of arbitrary depth and bit width. Automatically reduce BRAM usage through depth division, bit width division, and bit width folding.

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

开发者边车，github打不开，github加速，git clone加速，git release下载加速，stackoverflow加速

FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图像压缩。

Generic FIFO implementation with optional FWFT

All Algorithms implemented in Python

My Python Examples

HDL libraries and projects

Verilog code for VGA timing generator

《UVM实战》书本源代码和UVM 1.1d源码及Doc

Verification IP for I2C protocol

Absolute beginner's guide to the de10-nano

Simple and effective parallel CRC calculator written in synthesizable SystemVerilog

Open-source high performance AXI4-based HyperRAM memory controller

An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

MIPI CSI-2 RX

Examples and exercises for Practices of the Python Pro from Manning Books 🐍📘

A Linux-capable RISC-V multicore for and by the world

SystemVerilog parser library fully compliant with IEEE 1800-2017

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