Stars
CNN accelerator implemented with Spinal HDL
OpenTitan: Open source silicon root of trust
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
Tile based architecture designed for computing efficiency, scalability and generality
Our clone of https://github.com/bespoke-silicon-group/basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
Tengine is a lite, high performance, modular inference engine for embedded device
debauchee / barrier
Forked from symless/synergyOpen-source KVM software
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
vppillai / qemu
Forked from qemu/qemuOfficial QEMU mirror. Please see https://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
Simulation of a multiprocessor coherent cache using SystemC
Develop a Direct Memory Access Controller (DMA/DMAC) in SystemC.
YOLOv5 🚀 in PyTorch > ONNX > CoreML > TFLite
a training-target implementation of rv32im, designed to be simple and easy to understand
A FPGA friendly 32 bit RISC-V CPU implementation
Generator Bootcamp Material: Learn Chisel the Right Way
Open-source high-performance RISC-V processor
automatic-verilog based on vimscript