HLS for Networks-on-Chip

CNN accelerator implemented with Spinal HDL

uvm AXI BFM(bus functional model)

OpenTitan: Open source silicon root of trust

A4(An Amateur Alchemist’s Adventure)

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

General Purpose AXI Direct Memory Access

Tile based architecture designed for computing efficiency, scalability and generality

Our clone of https://github.com/bespoke-silicon-group/basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

Tengine is a lite, high performance, modular inference engine for embedded device

Open-source KVM software

RTL, Cmodel, and testbench for NVDLA

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

The OpenPiton Platform

Official QEMU mirror. Please see https://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

Simulation of a multiprocessor coherent cache using SystemC

Develop a Direct Memory Access Controller (DMA/DMAC) in SystemC.

YOLOv5 🚀 in PyTorch > ONNX > CoreML > TFLite

a training-target implementation of rv32im, designed to be simple and easy to understand

A FPGA friendly 32 bit RISC-V CPU implementation

xkISP：Xinkai ISP IP Core (HLS)

Generator Bootcamp Material: Learn Chisel the Right Way

Open-source high-performance RISC-V processor

automatic-verilog based on vimscript

OpenXuantie - OpenC906 Core

OpenXuantie - OpenC910 Core

菜鸡非科班转互联网开发的一些历程