mlx5: DR, Add sw-encap icm pool

There is a new ICM area for SW owned encap actions. This patch adds the memory pool to manage the new ICM memory type. Signed-off-by: Shun Hao <[email protected]> Reviewed-by: Yevgeny Kliteynik <[email protected]> Signed-off-by: Yishai Hadas <[email protected]>
linux-rdma · Dec 14, 2023 · 66f170e · 66f170e
1 parent e7c2d17
commit 66f170e
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Showing 5 changed files with 97 additions and 3 deletions.
diff --git a/providers/mlx5/dr_devx.c b/providers/mlx5/dr_devx.c
@@ -328,6 +328,8 @@ int dr_devx_query_device(struct ibv_context *ctx, struct dr_devx_caps *caps)
  return err;
  }
 
+ caps->max_encap_size = DEVX_GET(query_hca_cap_out, out,
+ capability.flow_table_nic_cap.max_encap_header_size);
  caps->nic_rx_drop_address = DEVX_GET64(query_hca_cap_out, out,
  capability.flow_table_nic_cap.
  sw_steering_nic_rx_action_drop_icm_address);
@@ -437,6 +439,15 @@ int dr_devx_query_device(struct ibv_context *ctx, struct dr_devx_caps *caps)
  DEVX_GET64(query_hca_cap_out, out,
  capability.device_mem_cap.header_modify_pattern_sw_icm_start_address);
 
+ caps->log_sw_encap_icm_size =
+ DEVX_GET(query_hca_cap_out, out,
+ capability.device_mem_cap.log_indirect_encap_sw_icm_size);
+
+ if (caps->log_sw_encap_icm_size)
+ caps->indirect_encap_icm_base =
+ DEVX_GET64(query_hca_cap_out, out,
+ capability.device_mem_cap.indirect_encap_icm_base);
+
  /* RoCE caps */
  if (roce) {
  err = dr_devx_query_nic_vport_context(ctx, &caps->roce_caps.roce_en);

diff --git a/providers/mlx5/dr_domain.c b/providers/mlx5/dr_domain.c
@@ -41,6 +41,34 @@ enum {
  MLX5DV_DR_DOMAIN_SYNC_FLAGS_MEM),
 };
 
+bool dr_domain_is_support_sw_encap(struct mlx5dv_dr_domain *dmn)
+{
+ return !!dmn->info.caps.log_sw_encap_icm_size;
+}
+
+static int dr_domain_init_sw_encap_resources(struct mlx5dv_dr_domain *dmn)
+{
+ if (!dr_domain_is_support_sw_encap(dmn))
+ return 0;
+
+ dmn->encap_icm_pool = dr_icm_pool_create(dmn, DR_ICM_TYPE_ENCAP);
+ if (!dmn->encap_icm_pool) {
+ dr_dbg(dmn, "Couldn't get sw-encap icm memory for %s\n",
+ ibv_get_device_name(dmn->ctx->device));
+ return errno;
+ }
+
+ return 0;
+}
+
+static void dr_domain_destroy_sw_encap_resources(struct mlx5dv_dr_domain *dmn)
+{
+ if (!dr_domain_is_support_sw_encap(dmn))
+ return;
+
+ dr_icm_pool_destroy(dmn->encap_icm_pool);
+}
+
 bool dr_domain_is_support_modify_hdr_cache(struct mlx5dv_dr_domain *dmn)
 {
  return dmn->info.caps.sw_format_ver >= MLX5_HW_CONNECTX_6DX &&
@@ -110,15 +138,24 @@ static int dr_domain_init_resources(struct mlx5dv_dr_domain *dmn)
  }
  }
 
+ ret = dr_domain_init_sw_encap_resources(dmn);
+ if (ret) {
+ dr_dbg(dmn, "Couldn't create sw-encap resource for %s\n",
+ ibv_get_device_name(dmn->ctx->device));
+ goto free_modify_header_ptrn_arg_mngr;
+ }
+
  ret = dr_send_ring_alloc(dmn);
  if (ret) {
  dr_dbg(dmn, "Couldn't create send-ring for %s\n",
  ibv_get_device_name(dmn->ctx->device));
- goto free_modify_header_ptrn_arg_mngr;
+ goto free_sw_encap_resources;
  }
 
  return 0;
 
+free_sw_encap_resources:
+ dr_domain_destroy_sw_encap_resources(dmn);
 free_modify_header_ptrn_arg_mngr:
  dr_ptrn_mngr_destroy(dmn->modify_header_ptrn_mngr);
  dr_arg_mngr_destroy(dmn->modify_header_arg_mngr);
@@ -136,6 +173,7 @@ static int dr_domain_init_resources(struct mlx5dv_dr_domain *dmn)
 static void dr_free_resources(struct mlx5dv_dr_domain *dmn)
 {
  dr_send_ring_free(dmn);
+ dr_domain_destroy_sw_encap_resources(dmn);
  dr_ptrn_mngr_destroy(dmn->modify_header_ptrn_mngr);
  dr_arg_mngr_destroy(dmn->modify_header_arg_mngr);
  dr_icm_pool_destroy(dmn->action_icm_pool);
@@ -446,6 +484,15 @@ static int dr_domain_check_icm_memory_caps(struct mlx5dv_dr_domain *dmn)
  dmn->info.max_log_modify_hdr_pattern_icm_sz = DR_CHUNK_SIZE_4K;
  }
 
+ if (dr_domain_is_support_sw_encap(dmn)) {
+ if (dmn->info.caps.log_sw_encap_icm_size <
+ (DR_CHUNK_SIZE_4K + DR_SW_ENCAP_ENTRY_LOG_SIZE)) {
+ errno = ENOMEM;
+ return errno;
+ }
+ dmn->info.max_log_sw_encap_icm_sz = DR_CHUNK_SIZE_4K;
+ }
+
  return 0;
 }
 
@@ -555,6 +602,12 @@ int mlx5dv_dr_domain_sync(struct mlx5dv_dr_domain *dmn, uint32_t flags)
  return ret;
  }
 
+ if (dmn->encap_icm_pool) {
+ ret = dr_icm_pool_sync_pool(dmn->encap_icm_pool);
+ if (ret)
+ return ret;
+ }
+
  if (dmn->action_icm_pool) {
  ret = dr_icm_pool_sync_pool(dmn->action_icm_pool);
  if (ret)

diff --git a/providers/mlx5/dr_icm_pool.c b/providers/mlx5/dr_icm_pool.c
@@ -84,6 +84,10 @@ dr_icm_allocate_aligned_dm(struct dr_icm_pool *pool,
  /* Align base is 64B */
  log_align_base = ilog32(DR_ICM_MODIFY_HDR_ALIGN_BASE - 1);
  break;
+ case DR_ICM_TYPE_ENCAP:
+ mlx5_dm_attr.type = MLX5_IB_UAPI_DM_TYPE_ENCAP_SW_ICM;
+ log_align_base = DR_SW_ENCAP_ENTRY_LOG_SIZE;
+ break;
  default:
  assert(false);
  errno = EINVAL;
@@ -577,6 +581,11 @@ struct dr_icm_pool *dr_icm_pool_create(struct mlx5dv_dr_domain *dmn,
  pool->th = dr_icm_pool_chunk_size_to_byte(pool->max_log_chunk_sz,
  pool->icm_type) / 2;
  break;
+ case DR_ICM_TYPE_ENCAP:
+ pool->max_log_chunk_sz = dmn->info.max_log_sw_encap_icm_sz;
+ pool->th = dr_icm_pool_chunk_size_to_byte(pool->max_log_chunk_sz,
+ pool->icm_type) / 2;
+ break;
  default:
  assert(false);
  }

diff --git a/providers/mlx5/mlx5_ifc.h b/providers/mlx5/mlx5_ifc.h
@@ -384,7 +384,8 @@ struct mlx5_ifc_device_mem_cap_bits {
  u8 log_sw_icm_alloc_granularity[0x6];
  u8 log_steering_sw_icm_size[0x8];
 
- u8 reserved_at_120[0x18];
+ u8 log_indirect_encap_sw_icm_size[0x8];
+ u8 reserved_at_128[0x10];
  u8 log_header_modify_pattern_sw_icm_size[0x8];
 
  u8 header_modify_sw_icm_start_address[0x40];
@@ -393,7 +394,13 @@ struct mlx5_ifc_device_mem_cap_bits {
 
  u8 header_modify_pattern_sw_icm_start_address[0x40];
 
- u8 reserved_at_200[0x600];
+ u8 reserved_at_200[0x40];
+
+ u8 indirect_encap_sw_icm_start_address[0x40];
+
+ u8 indirect_encap_icm_base[0x40];
+
+ u8 reserved_at_2c0[0x540];
 };
 
 struct mlx5_ifc_flow_table_fields_supported_bits {

diff --git a/providers/mlx5/mlx5dv_dr.h b/providers/mlx5/mlx5dv_dr.h
@@ -98,6 +98,7 @@ enum dr_icm_type {
  DR_ICM_TYPE_STE,
  DR_ICM_TYPE_MODIFY_ACTION,
  DR_ICM_TYPE_MODIFY_HDR_PTRN,
+ DR_ICM_TYPE_ENCAP,
  DR_ICM_TYPE_MAX,
 };
 
@@ -139,6 +140,11 @@ enum {
  DR_MODIFY_ACTION_LOG_SIZE = 3,
 };
 
+enum {
+ DR_SW_ENCAP_ENTRY_SIZE = 64,
+ DR_SW_ENCAP_ENTRY_LOG_SIZE = 6,
+};
+
 enum dr_matcher_criteria {
  DR_MATCHER_CRITERIA_EMPTY = 0,
  DR_MATCHER_CRITERIA_OUTER = 1 << 0,
@@ -941,6 +947,9 @@ struct dr_devx_caps {
  uint64_t hdr_modify_icm_addr;
  uint32_t log_modify_pattern_icm_size;
  uint64_t hdr_modify_pattern_icm_addr;
+ uint64_t indirect_encap_icm_base;
+ uint32_t log_sw_encap_icm_size;
+ uint16_t max_encap_size;
  uint32_t flex_protocols;
  uint8_t flex_parser_header_modify;
  uint8_t flex_parser_id_icmp_dw0;
@@ -1051,6 +1060,7 @@ struct dr_domain_info {
  uint32_t max_log_action_icm_sz;
  uint32_t max_log_modify_hdr_pattern_icm_sz;
  uint32_t max_log_sw_icm_rehash_sz;
+ uint32_t max_log_sw_encap_icm_sz;
  uint32_t max_send_size;
  struct dr_domain_rx_tx rx;
  struct dr_domain_rx_tx tx;
@@ -1076,6 +1086,7 @@ struct mlx5dv_dr_domain {
  struct dr_icm_pool *action_icm_pool;
  struct dr_ptrn_mngr *modify_header_ptrn_mngr;
  struct dr_arg_mngr *modify_header_arg_mngr;
+ struct dr_icm_pool *encap_icm_pool;
  struct dr_send_ring *send_ring[DR_MAX_SEND_RINGS];
  struct dr_domain_info info;
  struct list_head tbl_list;
@@ -1424,6 +1435,8 @@ dr_icm_pool_dm_type_to_entry_size(enum dr_icm_type icm_type)
 {
  if (icm_type == DR_ICM_TYPE_STE)
  return DR_STE_SIZE;
+ else if (icm_type == DR_ICM_TYPE_ENCAP)
+ return DR_SW_ENCAP_ENTRY_SIZE;
 
  return DR_MODIFY_ACTION_SIZE;
 }
@@ -1759,6 +1772,7 @@ struct dr_arg_obj *dr_arg_get_obj(struct dr_arg_mngr *mngr,
  uint8_t *data);
 void dr_arg_put_obj(struct dr_arg_mngr *mngr, struct dr_arg_obj *arg_obj);
 uint32_t dr_arg_get_object_id(struct dr_arg_obj *arg_obj);
+bool dr_domain_is_support_sw_encap(struct mlx5dv_dr_domain *dmn);
 
 int dr_buddy_init(struct dr_icm_buddy_mem *buddy, uint32_t max_order);
 void dr_buddy_cleanup(struct dr_icm_buddy_mem *buddy);