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mlx5_ifc.h
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mlx5_ifc.h
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/*
* Copyright (c) 2019 Mellanox Technologies, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MLX5_IFC_H
#define MLX5_IFC_H
#define u8 uint8_t
enum mlx5_cap_mode {
HCA_CAP_OPMOD_GET_MAX = 0,
HCA_CAP_OPMOD_GET_CUR = 1,
};
enum {
MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
MLX5_CMD_OP_INIT_HCA = 0x102,
MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
MLX5_CMD_OP_ENABLE_HCA = 0x104,
MLX5_CMD_OP_QUERY_PAGES = 0x107,
MLX5_CMD_OP_MANAGE_PAGES = 0x108,
MLX5_CMD_OP_SET_HCA_CAP = 0x109,
MLX5_CMD_OP_QUERY_ISSI = 0x10a,
MLX5_CMD_OP_SET_ISSI = 0x10b,
MLX5_CMD_OP_CREATE_MKEY = 0x200,
MLX5_CMD_OP_DESTROY_MKEY = 0x202,
MLX5_CMD_OP_CREATE_EQ = 0x301,
MLX5_CMD_OP_DESTROY_EQ = 0x302,
MLX5_CMD_OP_CREATE_CQ = 0x400,
MLX5_CMD_OP_DESTROY_CQ = 0x401,
MLX5_CMD_OP_CREATE_QP = 0x500,
MLX5_CMD_OP_DESTROY_QP = 0x501,
MLX5_CMD_OP_RST2INIT_QP = 0x502,
MLX5_CMD_OP_INIT2RTR_QP = 0x503,
MLX5_CMD_OP_RTR2RTS_QP = 0x504,
MLX5_CMD_OP_RTS2RTS_QP = 0x505,
MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
MLX5_CMD_OP_2ERR_QP = 0x507,
MLX5_CMD_OP_2RST_QP = 0x50a,
MLX5_CMD_OP_QUERY_QP = 0x50b,
MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
MLX5_CMD_OP_CREATE_PSV = 0x600,
MLX5_CMD_OP_DESTROY_PSV = 0x601,
MLX5_CMD_OP_CREATE_SRQ = 0x700,
MLX5_CMD_OP_DESTROY_SRQ = 0x701,
MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
MLX5_CMD_OP_CREATE_DCT = 0x710,
MLX5_CMD_OP_DESTROY_DCT = 0x711,
MLX5_CMD_OP_QUERY_DCT = 0x713,
MLX5_CMD_OP_CREATE_XRQ = 0x717,
MLX5_CMD_OP_DESTROY_XRQ = 0x718,
MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
MLX5_CMD_OP_ALLOC_PD = 0x800,
MLX5_CMD_OP_DEALLOC_PD = 0x801,
MLX5_CMD_OP_ALLOC_UAR = 0x802,
MLX5_CMD_OP_DEALLOC_UAR = 0x803,
MLX5_CMD_OP_ACCESS_REG = 0x805,
MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
MLX5_CMD_OP_QUERY_LAG = 0x842,
MLX5_CMD_OP_CREATE_TIR = 0x900,
MLX5_CMD_OP_DESTROY_TIR = 0x902,
MLX5_CMD_OP_CREATE_SQ = 0x904,
MLX5_CMD_OP_MODIFY_SQ = 0x905,
MLX5_CMD_OP_DESTROY_SQ = 0x906,
MLX5_CMD_OP_CREATE_RQ = 0x908,
MLX5_CMD_OP_DESTROY_RQ = 0x90a,
MLX5_CMD_OP_CREATE_RMP = 0x90c,
MLX5_CMD_OP_DESTROY_RMP = 0x90e,
MLX5_CMD_OP_CREATE_TIS = 0x912,
MLX5_CMD_OP_MODIFY_TIS = 0x913,
MLX5_CMD_OP_DESTROY_TIS = 0x914,
MLX5_CMD_OP_QUERY_TIS = 0x915,
MLX5_CMD_OP_CREATE_RQT = 0x916,
MLX5_CMD_OP_DESTROY_RQT = 0x918,
MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
MLX5_CMD_OP_CREATE_FLOW_COUNTER = 0x939,
MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
MLX5_CMD_OP_CREATE_UMEM = 0xa08,
MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
MLX5_CMD_OP_SYNC_STEERING = 0xb00,
};
enum {
MLX5_CMD_STAT_OK = 0x0,
MLX5_CMD_STAT_INT_ERR = 0x1,
MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
MLX5_CMD_STAT_RES_BUSY = 0x6,
MLX5_CMD_STAT_LIM_ERR = 0x8,
MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
MLX5_CMD_STAT_IX_ERR = 0xa,
MLX5_CMD_STAT_NO_RES_ERR = 0xf,
MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
};
enum {
MLX5_PAGES_CANT_GIVE = 0,
MLX5_PAGES_GIVE = 1,
MLX5_PAGES_TAKE = 2,
};
enum {
MLX5_REG_HOST_ENDIANNESS = 0x7004,
};
enum {
MLX5_CAP_PORT_TYPE_IB = 0x0,
MLX5_CAP_PORT_TYPE_ETH = 0x1,
};
enum mlx5_event {
MLX5_EVENT_TYPE_CMD = 0x0a,
MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
};
enum {
MLX5_EQ_DOORBEL_OFFSET = 0x40,
};
enum {
OPCODE_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
};
enum {
MLX5_DB_BLUEFLAME_BUFFER_SIZE = 0x100,
};
struct mlx5_ifc_atomic_caps_bits {
u8 reserved_at_0[0x40];
u8 atomic_req_8B_endianness_mode[0x2];
u8 reserved_at_42[0x4];
u8 supported_atomic_req_8B_endianness_mode_1[0x1];
u8 reserved_at_47[0x19];
u8 reserved_at_60[0x20];
u8 reserved_at_80[0x10];
u8 atomic_operations[0x10];
u8 reserved_at_a0[0x10];
u8 atomic_size_qp[0x10];
u8 reserved_at_c0[0x10];
u8 atomic_size_dc[0x10];
u8 reserved_at_e0[0x1a0];
u8 fetch_add_pci_atomic[0x10];
u8 swap_pci_atomic[0x10];
u8 compare_swap_pci_atomic[0x10];
u8 reserved_at_2b0[0x550];
};
struct mlx5_ifc_roce_cap_bits {
u8 reserved_0[0x4];
u8 sw_r_roce_src_udp_port[0x1];
u8 fl_rc_qp_when_roce_disabled[0x1];
u8 fl_rc_qp_when_roce_enabled[0x1];
u8 reserved_at_7[0x17];
u8 qp_ts_format[0x2];
u8 reserved_at_20[0x7e0];
};
enum {
MLX5_MULTI_PATH_FT_MAX_LEVEL = 64,
};
struct mlx5_ifc_flow_table_context_bits {
u8 reformat_en[0x1];
u8 decap_en[0x1];
u8 sw_owner[0x1];
u8 termination_table[0x1];
u8 table_miss_action[0x4];
u8 level[0x8];
u8 reserved_at_10[0x8];
u8 log_size[0x8];
u8 reserved_at_20[0x8];
u8 table_miss_id[0x18];
u8 reserved_at_40[0x8];
u8 lag_master_next_table_id[0x18];
u8 reserved_at_60[0x60];
u8 sw_owner_icm_root_1[0x40];
u8 sw_owner_icm_root_0[0x40];
};
struct mlx5_ifc_create_flow_table_in_bits {
u8 opcode[0x10];
u8 uid[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 other_vport[0x1];
u8 reserved_at_41[0xf];
u8 vport_number[0x10];
u8 reserved_at_60[0x20];
u8 table_type[0x8];
u8 reserved_at_88[0x18];
u8 reserved_at_a0[0x20];
struct mlx5_ifc_flow_table_context_bits flow_table_context;
};
struct mlx5_ifc_create_flow_table_out_bits {
u8 status[0x8];
u8 icm_address_63_40[0x18];
u8 syndrome[0x20];
u8 icm_address_39_32[0x8];
u8 table_id[0x18];
u8 icm_address_31_0[0x20];
};
struct mlx5_ifc_destroy_flow_table_in_bits {
u8 opcode[0x10];
u8 reserved_at_10[0x10];
u8 reserved_at_20[0x20];
u8 other_vport[0x1];
u8 reserved_at_41[0xf];
u8 vport_number[0x10];
u8 reserved_at_60[0x20];
u8 table_type[0x8];
u8 reserved_at_88[0x18];
u8 reserved_at_a0[0x8];
u8 table_id[0x18];
u8 reserved_at_c0[0x140];
};
struct mlx5_ifc_query_flow_table_in_bits {
u8 opcode[0x10];
u8 reserved_at_10[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 reserved_at_40[0x40];
u8 table_type[0x8];
u8 reserved_at_88[0x18];
u8 reserved_at_a0[0x8];
u8 table_id[0x18];
u8 reserved_at_c0[0x140];
};
struct mlx5_ifc_query_flow_table_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
u8 syndrome[0x20];
u8 reserved_at_40[0x80];
struct mlx5_ifc_flow_table_context_bits flow_table_context;
};
struct mlx5_ifc_sync_steering_in_bits {
u8 opcode[0x10];
u8 uid[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 reserved_at_40[0xc0];
};
struct mlx5_ifc_sync_steering_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
};
struct mlx5_ifc_device_mem_cap_bits {
u8 memic[0x1];
u8 reserved_at_1[0x1f];
u8 reserved_at_20[0xb];
u8 log_min_memic_alloc_size[0x5];
u8 reserved_at_30[0x8];
u8 log_max_memic_addr_alignment[0x8];
u8 memic_bar_start_addr[0x40];
u8 memic_bar_size[0x20];
u8 max_memic_size[0x20];
u8 steering_sw_icm_start_address[0x40];
u8 reserved_at_100[0x8];
u8 log_header_modify_sw_icm_size[0x8];
u8 reserved_at_110[0x2];
u8 log_sw_icm_alloc_granularity[0x6];
u8 log_steering_sw_icm_size[0x8];
u8 log_indirect_encap_sw_icm_size[0x8];
u8 reserved_at_128[0x10];
u8 log_header_modify_pattern_sw_icm_size[0x8];
u8 header_modify_sw_icm_start_address[0x40];
u8 reserved_at_180[0x40];
u8 header_modify_pattern_sw_icm_start_address[0x40];
u8 reserved_at_200[0x40];
u8 indirect_encap_sw_icm_start_address[0x40];
u8 indirect_encap_icm_base[0x40];
u8 reserved_at_2c0[0x540];
};
struct mlx5_ifc_flow_table_fields_supported_bits {
u8 outer_dmac[0x1];
u8 outer_smac[0x1];
u8 outer_ether_type[0x1];
u8 outer_ip_version[0x1];
u8 outer_first_prio[0x1];
u8 outer_first_cfi[0x1];
u8 outer_first_vid[0x1];
u8 outer_ipv4_ttl[0x1];
u8 outer_second_prio[0x1];
u8 outer_second_cfi[0x1];
u8 outer_second_vid[0x1];
u8 outer_ipv6_flow_label[0x1];
u8 outer_sip[0x1];
u8 outer_dip[0x1];
u8 outer_frag[0x1];
u8 outer_ip_protocol[0x1];
u8 outer_ip_ecn[0x1];
u8 outer_ip_dscp[0x1];
u8 outer_udp_sport[0x1];
u8 outer_udp_dport[0x1];
u8 outer_tcp_sport[0x1];
u8 outer_tcp_dport[0x1];
u8 outer_tcp_flags[0x1];
u8 outer_gre_protocol[0x1];
u8 outer_gre_key[0x1];
u8 outer_vxlan_vni[0x1];
u8 outer_geneve_vni[0x1];
u8 outer_geneve_oam[0x1];
u8 outer_geneve_protocol_type[0x1];
u8 outer_geneve_opt_len[0x1];
u8 source_vhca_port[0x1];
u8 source_eswitch_port[0x1];
u8 inner_dmac[0x1];
u8 inner_smac[0x1];
u8 inner_ether_type[0x1];
u8 inner_ip_version[0x1];
u8 inner_first_prio[0x1];
u8 inner_first_cfi[0x1];
u8 inner_first_vid[0x1];
u8 inner_ipv4_ttl[0x1];
u8 inner_second_prio[0x1];
u8 inner_second_cfi[0x1];
u8 inner_second_vid[0x1];
u8 inner_ipv6_flow_label[0x1];
u8 inner_sip[0x1];
u8 inner_dip[0x1];
u8 inner_frag[0x1];
u8 inner_ip_protocol[0x1];
u8 inner_ip_ecn[0x1];
u8 inner_ip_dscp[0x1];
u8 inner_udp_sport[0x1];
u8 inner_udp_dport[0x1];
u8 inner_tcp_sport[0x1];
u8 inner_tcp_dport[0x1];
u8 inner_tcp_flags[0x1];
u8 reserved_at_37[0x7];
u8 metadata_reg_b[0x1];
u8 metadata_reg_a[0x1];
u8 geneve_tlv_option_0_data[0x1];
u8 geneve_tlv_option_0_exist[0x1];
u8 reserved_at_42[0x3];
u8 outer_first_mpls_over_udp_ttl[0x1];
u8 outer_first_mpls_over_udp_s_bos[0x1];
u8 outer_first_mpls_over_udp_exp[0x1];
u8 outer_first_mpls_over_udp_label[0x1];
u8 outer_first_mpls_over_gre_ttl[0x1];
u8 outer_first_mpls_over_gre_s_bos[0x1];
u8 outer_first_mpls_over_gre_exp[0x1];
u8 outer_first_mpls_over_gre_label[0x1];
u8 inner_first_mpls_ttl[0x1];
u8 inner_first_mpls_s_bos[0x1];
u8 inner_first_mpls_exp[0x1];
u8 inner_first_mpls_label[0x1];
u8 outer_first_mpls_ttl[0x1];
u8 outer_first_mpls_s_bos[0x1];
u8 outer_first_mpls_exp[0x1];
u8 outer_first_mpls_label[0x1];
u8 outer_emd_tag[0x1];
u8 inner_esp_spi[0x1];
u8 outer_esp_spi[0x1];
u8 inner_ipv6_hop_limit[0x1];
u8 outer_ipv6_hop_limit[0x1];
u8 bth_dst_qp[0x1];
u8 inner_first_svlan[0x1];
u8 inner_second_svlan[0x1];
u8 outer_first_svlan[0x1];
u8 outer_second_svlan[0x1];
u8 source_sqn[0x1];
u8 reserved_at_60[0x20];
};
struct mlx5_ifc_dr_match_spec_bits {
u8 smac_47_16[0x20];
u8 smac_15_0[0x10];
u8 ethertype[0x10];
u8 dmac_47_16[0x20];
u8 dmac_15_0[0x10];
u8 first_prio[0x3];
u8 first_cfi[0x1];
u8 first_vid[0xc];
u8 ip_protocol[0x8];
u8 ip_dscp[0x6];
u8 ip_ecn[0x2];
u8 cvlan_tag[0x1];
u8 svlan_tag[0x1];
u8 frag[0x1];
u8 ip_version[0x4];
u8 tcp_flags[0x9];
u8 tcp_sport[0x10];
u8 tcp_dport[0x10];
u8 reserved_at_c0[0x10];
u8 ipv4_ihl[0x4];
u8 l3_ok[0x1];
u8 l4_ok[0x1];
u8 ipv4_checksum_ok[0x1];
u8 l4_checksum_ok[0x1];
u8 ip_ttl_hoplimit[0x8];
u8 udp_sport[0x10];
u8 udp_dport[0x10];
u8 src_ip_127_96[0x20];
u8 src_ip_95_64[0x20];
u8 src_ip_63_32[0x20];
u8 src_ip_31_0[0x20];
u8 dst_ip_127_96[0x20];
u8 dst_ip_95_64[0x20];
u8 dst_ip_63_32[0x20];
u8 dst_ip_31_0[0x20];
};
struct mlx5_ifc_dr_match_set_misc_bits {
u8 gre_c_present[0x1];
u8 bth_a[0x1];
u8 gre_k_present[0x1];
u8 gre_s_present[0x1];
u8 source_vhca_port[0x4];
u8 source_sqn[0x18];
u8 source_eswitch_owner_vhca_id[0x10];
u8 source_port[0x10];
u8 outer_second_prio[0x3];
u8 outer_second_cfi[0x1];
u8 outer_second_vid[0xc];
u8 inner_second_prio[0x3];
u8 inner_second_cfi[0x1];
u8 inner_second_vid[0xc];
u8 outer_second_cvlan_tag[0x1];
u8 inner_second_cvlan_tag[0x1];
u8 outer_second_svlan_tag[0x1];
u8 inner_second_svlan_tag[0x1];
u8 outer_emd_tag[0x1];
u8 reserved_at_65[0xb];
u8 gre_protocol[0x10];
u8 gre_key_h[0x18];
u8 gre_key_l[0x8];
u8 vxlan_vni[0x18];
u8 bth_opcode[0x8];
u8 geneve_vni[0x18];
u8 reserved_at_e4[0x6];
u8 geneve_tlv_option_0_exist[0x1];
u8 geneve_oam[0x1];
u8 reserved_at_ec[0xc];
u8 outer_ipv6_flow_label[0x14];
u8 reserved_at_100[0xc];
u8 inner_ipv6_flow_label[0x14];
u8 reserved_at_120[0xa];
u8 geneve_opt_len[0x6];
u8 geneve_protocol_type[0x10];
u8 reserved_at_140[0x8];
u8 bth_dst_qp[0x18];
u8 inner_esp_spi[0x20];
u8 outer_esp_spi[0x20];
u8 reserved_at_1a0[0x20];
u8 reserved_at_1c0[0x20];
u8 reserved_at_1e0[0x20];
};
struct mlx5_ifc_dr_match_set_misc2_bits {
u8 outer_first_mpls_label[0x14];
u8 outer_first_mpls_exp[0x3];
u8 outer_first_mpls_s_bos[0x1];
u8 outer_first_mpls_ttl[0x8];
u8 inner_first_mpls_label[0x14];
u8 inner_first_mpls_exp[0x3];
u8 inner_first_mpls_s_bos[0x1];
u8 inner_first_mpls_ttl[0x8];
u8 outer_first_mpls_over_gre_label[0x14];
u8 outer_first_mpls_over_gre_exp[0x3];
u8 outer_first_mpls_over_gre_s_bos[0x1];
u8 outer_first_mpls_over_gre_ttl[0x8];
u8 outer_first_mpls_over_udp_label[0x14];
u8 outer_first_mpls_over_udp_exp[0x3];
u8 outer_first_mpls_over_udp_s_bos[0x1];
u8 outer_first_mpls_over_udp_ttl[0x8];
u8 metadata_reg_c_7[0x20];
u8 metadata_reg_c_6[0x20];
u8 metadata_reg_c_5[0x20];
u8 metadata_reg_c_4[0x20];
u8 metadata_reg_c_3[0x20];
u8 metadata_reg_c_2[0x20];
u8 metadata_reg_c_1[0x20];
u8 metadata_reg_c_0[0x20];
u8 metadata_reg_a[0x20];
u8 reserved_at_1a0[0x20];
u8 reserved_at_1c0[0x20];
u8 reserved_at_1e0[0x20];
};
struct mlx5_ifc_dr_match_set_misc3_bits {
u8 inner_tcp_seq_num[0x20];
u8 outer_tcp_seq_num[0x20];
u8 inner_tcp_ack_num[0x20];
u8 outer_tcp_ack_num[0x20];
u8 reserved_at_80[0x8];
u8 outer_vxlan_gpe_vni[0x18];
u8 outer_vxlan_gpe_next_protocol[0x8];
u8 outer_vxlan_gpe_flags[0x8];
u8 reserved_at_b0[0x10];
u8 icmp_header_data[0x20];
u8 icmpv6_header_data[0x20];
u8 icmp_type[0x8];
u8 icmp_code[0x8];
u8 icmpv6_type[0x8];
u8 icmpv6_code[0x8];
u8 geneve_tlv_option_0_data[0x20];
u8 gtpu_teid[0x20];
u8 gtpu_msg_type[0x8];
u8 gtpu_msg_flags[0x8];
u8 reserved_at_170[0x10];
u8 gtpu_dw_2[0x20];
u8 gtpu_first_ext_dw_0[0x20];
u8 gtpu_dw_0[0x20];
u8 reserved_at_1e0[0x20];
};
struct mlx5_ifc_dr_match_set_misc4_bits {
u8 prog_sample_field_value_0[0x20];
u8 prog_sample_field_id_0[0x20];
u8 prog_sample_field_value_1[0x20];
u8 prog_sample_field_id_1[0x20];
u8 prog_sample_field_value_2[0x20];
u8 prog_sample_field_id_2[0x20];
u8 prog_sample_field_value_3[0x20];
u8 prog_sample_field_id_3[0x20];
u8 prog_sample_field_value_4[0x20];
u8 prog_sample_field_id_4[0x20];
u8 prog_sample_field_value_5[0x20];
u8 prog_sample_field_id_5[0x20];
u8 prog_sample_field_value_6[0x20];
u8 prog_sample_field_id_6[0x20];
u8 prog_sample_field_value_7[0x20];
u8 prog_sample_field_id_7[0x20];
};
struct mlx5_ifc_dr_match_set_misc5_bits {
u8 macsec_tag_0[0x20];
u8 macsec_tag_1[0x20];
u8 macsec_tag_2[0x20];
u8 macsec_tag_3[0x20];
u8 tunnel_header_0[0x20];
u8 tunnel_header_1[0x20];
u8 tunnel_header_2[0x20];
u8 tunnel_header_3[0x20];
u8 reserved_at_100[0x20];
u8 reserved_at_120[0x20];
u8 reserved_at_140[0x20];
u8 reserved_at_160[0x20];
u8 reserved_at_180[0x20];
u8 reserved_at_1a0[0x20];
u8 reserved_at_1c0[0x20];
u8 reserved_at_1e0[0x20];
};
struct mlx5_ifc_dr_match_param_bits {
struct mlx5_ifc_dr_match_spec_bits outer;
struct mlx5_ifc_dr_match_set_misc_bits misc;
struct mlx5_ifc_dr_match_spec_bits inner;
struct mlx5_ifc_dr_match_set_misc2_bits misc2;
struct mlx5_ifc_dr_match_set_misc3_bits misc3;
struct mlx5_ifc_dr_match_set_misc4_bits misc4;
struct mlx5_ifc_dr_match_set_misc5_bits misc5;
};
struct mlx5_ifc_flow_table_prop_layout_bits {
u8 ft_support[0x1];
u8 flow_tag[0x1];
u8 flow_counter[0x1];
u8 flow_modify_en[0x1];
u8 modify_root[0x1];
u8 identified_miss_table[0x1];
u8 flow_table_modify[0x1];
u8 reformat[0x1];
u8 decap[0x1];
u8 reset_root_to_default[0x1];
u8 pop_vlan[0x1];
u8 push_vlan[0x1];
u8 fpga_vendor_acceleration[0x1];
u8 pop_vlan_2[0x1];
u8 push_vlan_2[0x1];
u8 reformat_and_vlan_action[0x1];
u8 modify_and_vlan_action[0x1];
u8 sw_owner[0x1];
u8 reformat_l3_tunnel_to_l2[0x1];
u8 reformat_l2_to_l3_tunnel[0x1];
u8 reformat_and_modify_action[0x1];
u8 reserved_at_15[0x9];
u8 sw_owner_v2[0x1];
u8 reserved_at_1f[0x1];
u8 reserved_at_20[0x2];
u8 log_max_ft_size[0x6];
u8 log_max_modify_header_context[0x8];
u8 max_modify_header_actions[0x8];
u8 max_ft_level[0x8];
u8 reserved_at_40[0x10];
u8 metadata_reg_b_width[0x8];
u8 metadata_reg_a_width[0x8];
u8 reserved_at_60[0x18];
u8 log_max_ft_num[0x8];
u8 reserved_at_80[0x10];
u8 log_max_flow_counter[0x8];
u8 log_max_destination[0x8];
u8 reserved_at_a0[0x18];
u8 log_max_flow[0x8];
u8 reserved_at_c0[0x40];
struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
};
enum {
MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4,
mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5,
MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
MLX5_FLEX_PARSER_GENEVE_OPT_0_ENABLED = 1 << 10,
MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11,
MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16,
MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18,
MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19,
};
enum mlx5_ifc_steering_format_version {
MLX5_HW_CONNECTX_5 = 0x0,
MLX5_HW_CONNECTX_6DX = 0x1,
MLX5_HW_CONNECTX_7 = 0x2,
};
enum mlx5_ifc_ste_v1_modify_hdr_offset {
MLX5_MODIFY_HEADER_V1_QW_OFFSET = 0x20,
};
struct mlx5_ifc_cmd_hca_cap_bits {
u8 access_other_hca_roce[0x1];
u8 reserved_at_1[0x1e];
u8 vhca_resource_manager[0x1];
u8 hca_cap_2[0x1];
u8 reserved_at_21[0xf];
u8 vhca_id[0x10];
u8 reserved_at_40[0x20];
u8 reserved_at_60[0x2];
u8 qp_data_in_order[0x1];
u8 reserved_at_63[0x8];
u8 log_dma_mmo_max_size[0x5];
u8 reserved_at_70[0x10];
u8 log_max_srq_sz[0x8];
u8 log_max_qp_sz[0x8];
u8 reserved_at_90[0x3];
u8 isolate_vl_tc_new[0x1];
u8 reserved_at_94[0x4];
u8 prio_tag_required[0x1];
u8 reserved_at_99[0x2];
u8 log_max_qp[0x5];
u8 reserved_at_a0[0xb];
u8 log_max_srq[0x5];
u8 reserved_at_b0[0x10];
u8 reserved_at_c0[0x8];
u8 log_max_cq_sz[0x8];
u8 reserved_at_d0[0xb];
u8 log_max_cq[0x5];
u8 log_max_eq_sz[0x8];
u8 relaxed_ordering_write[0x1];
u8 reserved_at_e9[0x1];
u8 log_max_mkey[0x6];
u8 tunneled_atomic[0x1];
u8 as_notify[0x1];
u8 m_pci_port[0x1];
u8 m_vhca_mk[0x1];
u8 cmd_on_behalf[0x1];
u8 device_emulation_manager[0x1];
u8 terminate_scatter_list_mkey[0x1];
u8 repeated_mkey[0x1];
u8 dump_fill_mkey[0x1];
u8 reserved_at_f9[0x3];
u8 log_max_eq[0x4];
u8 max_indirection[0x8];
u8 fixed_buffer_size[0x1];
u8 log_max_mrw_sz[0x7];
u8 force_teardown[0x1];
u8 fast_teardown[0x1];
u8 log_max_bsf_list_size[0x6];
u8 umr_extended_translation_offset[0x1];
u8 null_mkey[0x1];
u8 log_max_klm_list_size[0x6];
u8 reserved_at_120[0x2];
u8 qpc_extension[0x1];
u8 reserved_at_123[0x7];
u8 log_max_ra_req_dc[0x6];
u8 reserved_at_130[0xa];
u8 log_max_ra_res_dc[0x6];
u8 reserved_at_140[0x7];
u8 sig_crc64_xp10[0x1];
u8 sig_crc32c[0x1];
u8 reserved_at_149[0x1];
u8 log_max_ra_req_qp[0x6];
u8 reserved_at_150[0x1];
u8 rts2rts_qp_udp_sport[0x1];
u8 rts2rts_lag_tx_port_affinity[0x1];
u8 dma_mmo_sq[0x1];
u8 reserved_at_154[0x6];
u8 log_max_ra_res_qp[0x6];
u8 end_pad[0x1];
u8 cc_query_allowed[0x1];
u8 cc_modify_allowed[0x1];
u8 start_pad[0x1];
u8 cache_line_128byte[0x1];
u8 gid_table_size_ro[0x1];
u8 pkey_table_size_ro[0x1];
u8 reserved_at_167[0x1];
u8 rnr_nak_q_counters[0x1];
u8 rts2rts_qp_counters_set_id[0x1];
u8 rts2rts_qp_dscp[0x1];
u8 reserved_at_16b[0x4];
u8 qcam_reg[0x1];
u8 gid_table_size[0x10];
u8 out_of_seq_cnt[0x1];
u8 vport_counters[0x1];
u8 retransmission_q_counters[0x1];
u8 debug[0x1];
u8 modify_rq_counters_set_id[0x1];
u8 rq_delay_drop[0x1];
u8 max_qp_cnt[0xa];
u8 pkey_table_size[0x10];
u8 vport_group_manager[0x1];
u8 vhca_group_manager[0x1];
u8 ib_virt[0x1];
u8 eth_virt[0x1];
u8 vnic_env_queue_counters[0x1];
u8 ets[0x1];
u8 nic_flow_table[0x1];
u8 eswitch_manager[0x1];
u8 device_memory[0x1];
u8 mcam_reg[0x1];
u8 pcam_reg[0x1];
u8 local_ca_ack_delay[0x5];
u8 port_module_event[0x1];
u8 enhanced_retransmission_q_counters[0x1];
u8 port_checks[0x1];
u8 pulse_gen_control[0x1];
u8 disable_link_up_by_init_hca[0x1];
u8 beacon_led[0x1];
u8 port_type[0x2];
u8 num_ports[0x8];
u8 reserved_at_1c0[0x1];
u8 pps[0x1];
u8 pps_modify[0x1];
u8 log_max_msg[0x5];
u8 multi_path_xrc_rdma[0x1];
u8 multi_path_dc_rdma[0x1];
u8 multi_path_rc_rdma[0x1];
u8 traffic_fast_control[0x1];
u8 max_tc[0x4];
u8 temp_warn_event[0x1];
u8 dcbx[0x1];
u8 general_notification_event[0x1];
u8 multi_prio_sq[0x1];
u8 afu_owner[0x1];
u8 fpga[0x1];
u8 rol_s[0x1];
u8 rol_g[0x1];
u8 ib_port_sniffer[0x1];
u8 wol_s[0x1];
u8 wol_g[0x1];
u8 wol_a[0x1];
u8 wol_b[0x1];
u8 wol_m[0x1];
u8 wol_u[0x1];
u8 wol_p[0x1];
u8 stat_rate_support[0x10];
u8 sig_block_4048[0x1];