kbbuch / LC3-Verification Public

Verification of a 5 stage LC3 pipelined CPU with System Verilog and Mentor Graphics ModelSim

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
Control_Stage.sv		Control_Stage.sv
Coverage.sv		Coverage.sv
Driver.sv		Driver.sv
Environment.sv		Environment.sv
Generator.sv		Generator.sv
Instruction.sv		Instruction.sv
MemAccess_GoldRef.sv		MemAccess_GoldRef.sv
MemAccess_Monitor.sv		MemAccess_Monitor.sv
README.md		README.md
Report_verif_group14.pdf		Report_verif_group14.pdf
compile.do		compile.do
decodeblock.sv		decodeblock.sv
executeblock.sv		executeblock.sv
fetchj2.sv		fetchj2.sv
final_submission_coverage.ucdb		final_submission_coverage.ucdb
param_mod.sv		param_mod.sv
params.sv		params.sv
project.LC3_testbench.sv		project.LC3_testbench.sv
project.if_finalizing.sv		project.if_finalizing.sv
project.test_top.sv		project.test_top.sv
tempinterface.sv		tempinterface.sv
writeback.sv		writeback.sv

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