BS EE grad student with focus: digital/VLSI.
Interests: automated testing, digital design, HDL, ASIC, Verilog, Systemverilog, Cadence Virtuoso, Python
- Portland, Oregon, U.S.A.
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ECE428___K-L_Tool Public
VLSI with CAD: Python program which accepts file input and determines the minimum cutset
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Senior project: Automated testing in Python for Django project
Python UpdatedDec 19, 2019