Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

SparseP is the first open-source Sparse Matrix Vector Multiplication (SpMV) software package for real-world Processing-In-Memory (PIM) architectures. SparseP is developed to evaluate and characteri…

IEEE 754 floating point library in system-verilog and vhdl

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Functional verification project for the CORE-V family of RISC-V cores.

The Horizon 2020 Open Transprecision Computing project

An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).

A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.

Open, Modular, Deep Learning Accelerator

A flush-reload side channel attack implementation

OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.

Contains the code examples from The UVM Primer Book sorted by chapters.

Generator Bootcamp Material: Learn Chisel the Right Way

NucleusRV - A 32-bit 5 staged pipelined risc-v core.

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Tile based architecture designed for computing efficiency, scalability and generality

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

A core language for rule-based hardware design 🦑

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

A self-contained online book containing a library of FPGA design modules and related coding/design guides.

SHAKTI Multiply-And-Accumulate Accelerator Network (SHAKTIMAAN), IITM's Deep Learning accelerator effort

RISC-V Assembly Programmer's Manual

10x faster matrix and vector operations