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@mit-han-lab
MIT HAN Lab mit-han-lab
Efficient AI Computing. PI: Song Han

MIT

@hlslibs
HLSLibs hlslibs
Open-Source High-Level Synthesis IP Libraries
@diwu1990
Di Wu (Dee Woo) diwu1990
Assistant Professor at UCF ECE

University of Central Florida

@open-neuromorphic
Open Neuromorphic open-neuromorphic
Neuromorphic Computing and Engineering Community
@UCLA-VAST
UCLA VAST Lab UCLA-VAST

Los Angeles, CA, U.S.

@govardhnn
Govardhan govardhnn

InCore Semiconductors

@sarabjeetsingh007
Sarabjeet Singh sarabjeetsingh007
PhD Student, University of Utah
@bespoke-silicon-group
Bespoke Silicon Group bespoke-silicon-group
Accelerating productive, PPA-optimal HW Design
@kssuraaj28
Suraaj K S kssuraaj28
PhD student @ Cornell CS

India

@vlsi-nanocomputing
VLSI Lab - Politecnico di Torino vlsi-nanocomputing
The VLSI group provides expertise in the field of emerging technologies, EDA and simulation tools, as well as the development of logic-in-memory architectures.

Italy

@rajesh-s
Rajesh Shashi Kumar rajesh-s
Contributions from my personal addresses are my own and not on behalf of my employer.
@aolofsson
Andreas Olofsson aolofsson
Reducing the barrier to silicon at Zero ASIC. Formerly @ DARPA, Adapteva, Analog Devices, Texas Instruments.

Zero ASIC Corporation Cambridge, MA, USA

@VLSIDA
VLSI Design & Automation Group VLSIDA
UC Santa Cruz VLSI Design and Automation research lab

Santa Cruz, CA

@esl-epfl
Embedded Systems Lab (ESL) - EPFL esl-epfl
Embedded Systems Laboratory (ESL) at École Polytechnique Fédérale de Lausanne (EPFL)

EPFL, Lausanne, Switzerland

@Anish-Saxena
Anish Saxena Anish-Saxena
CS PhD student at Georgia Tech. Interested in computer architecture, systems, and security.
@arjunmenonv
Arjun Menon Vadakkeveedu arjunmenonv
UG Senior, Electrical Engineering at IITM. My interests are in Computer Architecture & Digital VLSI. I also enjoy playing with Analog, DSP and Deep Learning.

Chennai, India

@asyncvlsi
Yale Asynchronous VLSI and Architecture Group asyncvlsi
Research group led by Rajit Manohar working on asynchronous digital circuits and systems
@sharc-lab
Sharc-Lab sharc-lab
Software/hardware Co-design Lab at Georgia Tech

Georgia

@remzi-arpacidusseau
Remzi Arpaci-Dusseau remzi-arpacidusseau
Remzi Arpaci-Dusseau is a full professor in the Computer Sciences department at the University of Wisconsin-Madison.

University of Wisconsin-Madison Madison, WI

@CoffeeBeforeArch
Nick CoffeeBeforeArch
Performance engineer that's always happy to answer questions!

Sunnyvale

@umd-memsys
University of Maryland Memory-Systems Research umd-memsys
University of Maryland Memory-Systems Research
@projf
Project F projf
FPGA and RISC-V Development
@raulbehl
raulbehl
Computer Architecture Enthusiast, Verilog & Assembly level programmer
@chipsalliance
CHIPS Alliance chipsalliance
Common Hardware for Interfaces, Processors and Systems
@rapidsai
RAPIDS rapidsai
Open GPU Data Science
@gthparch
High Performance Architecture Lab at GT gthparch
We focus on research which enables high-performance and energy-efficient computing from microarchitectures to compilers.
@pawks
Pawan Kumar Sanjaya pawks

University of Toronto

@doonny
Dong Wang doonny
Prof. at The Heterogeneous Computing Lab of Beijing Jiaotong University

Beijing Jiaotong University Beijing, China

@pmem
Persistent Memory Programming pmem
Libraries and Examples for Persistent Memory Programming
@avashist003
Abhishek Vashist avashist003

Rochester Institute of Technology Rochester, NY, USA

@scarv
SCARV scarv
a side-channel hardened RISC-V platform
@fengbintu
Fengbin Tu fengbintu
I'm an Assistant Professor at HKUST, with PhD degree from Tsinghua University. My research interests include AI Chip and Computing-In-Memory.

HKUST Hong Kong, China

@Wren6991
Luke Wren Wren6991
Interests: C, Verilog, Python Dislikes: C, Verilog, Python

Cambridge, UK

@PolyArch
PolyArch PolyArch
PolyArch Research Group
@mattvenn
matt venn mattvenn
Engineer and Science Communication. On a mission to make ASICs more accessible. YosysHQ & Tiny Tapeout founder member.

Valencia, Spain