Skip to content
View hacuit's full-sized avatar

Highlights

  • Pro
Block or Report

Block or report hacuit

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Starred repositories

Showing results

Small scale distributed training of sequential deep learning models, built on Numpy and MPI.

Python 77 3 Updated Oct 19, 2023

1.58-bit LLaMa model

Python 77 6 Updated Apr 3, 2024

SOTA low-bit LLM quantization (INT8/FP8/INT4/FP4/NF4) & sparsity; leading model compression techniques on TensorFlow, PyTorch, and ONNX Runtime

Python 2,106 249 Updated Aug 6, 2024

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

PHP 1 Updated Apr 4, 2022

에타 시간표 유사도 추천

JavaScript 1 2 Updated Dec 8, 2022

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

C 1,219 369 Updated Feb 14, 2022

Convolutional accelerator kernel, target ASIC & FPGA

Verilog 151 23 Updated Apr 10, 2023

OpenTitan: Open source silicon root of trust

SystemVerilog 2,462 736 Updated Aug 6, 2024

training labs and examples

SystemVerilog 388 173 Updated Aug 1, 2022

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

Verilog 78 11 Updated Sep 7, 2020

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,000 280 Updated Aug 6, 2024

Repository of Jupyter notebook tutorials for teaching the Deep Learning Course at the University of Amsterdam (MSc AI), Fall 2023

Jupyter Notebook 2,376 550 Updated Jun 10, 2024