Small SERV-based SoC primarily for OpenMPW tapeout

Primary GIT Repository for the Zephyr Project

CoreScore

Package manager and build abstraction tool for FPGA/ASIC development

SERV - The SErial RISC-V CPU

An awesome list of complex systems science resources

该仓库是 Tiniux OS v3.0.0 的注释版，供学习交流使用，本人会不断地维护注释质量。

Lightweight, Portable RTOS Scheduler

Program to optimize the design of DC-DC converter controllers

Synchronous DC/DC Buck Converter using GaN FETs

Model-Based Design of a DCDC Converter using Simulink, Simscape and Stateflow

This repository includes the works about design of DC/DC converter with suppy of 100W.

Simulator for DC-DC power converters

Collection of DC/DC Converters, Battery Chargers and Power Supplies

Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit

Python port of Prof. Boris Murmann's gm/ID Starter Kit

In this project I examined three different methods to monitor the heart activity. The "gold standard" is considered to be ECG, therefore the other 2 methods which are PCG and BCG are compared to th…

深度学习500问，以问答形式对常用的概率知识、线性代数、机器学习、深度学习、计算机视觉等热点问题进行阐述，以帮助自己及有需要的读者。 全书分为18个章节，50余万字。由于水平有限，书中不妥之处恳请广大读者批评指正。 未完待续............ 如有意合作，联系[email protected] 版权所有，违权必究 Tan 2018.06

Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

CNN acceleration on virtex-7 FPGA with verilog HDL

Verilog library for ASIC and FPGA designers

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

使用stm32F407芯片和ov7725摄像头对视频流进行图像处理，包括图像二值化，颜色识别等

Image Classification with STM32 using CIFAR-10 Dataset

image classifier on stm32