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Tsinghua University
- Ziqiang Science and Technology No.1 Building
- https://www.fuchuanpu.cn/
- https://orcid.org/0000-0003-4568-6125
- @ChuanpuFu
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Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
This repository contains the artifacts for the paper "Terrapin Attack: Breaking SSH Channel Integrity By Sequence Number Manipulation".
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An Efficient Design of Intelligent Network Data Plane
IPID Hash Collision TCP Side Channel Attack
Reduce false-positive alarms via voxel based point cloud analysis.
Hashed Lookup Table based Matrix Multiplication (halutmatmul) - Stella Nera accelerator
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
Minimal implementation of clipped objective Proximal Policy Optimization (PPO) in PyTorch
Do Switches Dream of Machine Learning?, HotNets 2019
PcapPlusPlus is a multiplatform C++ library for capturing, parsing and crafting of network packets. It is designed to be efficient, powerful and easy to use. It provides C++ wrappers for the most p…
RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
3D Bin Packing improvements based on https://github.com/enzoruiz/3dbinpacking
Flow Interaction Graph based attack traffic detection system.
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Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
Realtime Robust Malicious Traffic Detection via Frequency Domain Analysis
Verilog Ethernet components for FPGA implementation
A facebook bot to scrap, post, spam and more without the facebook API