Verilog library for ASIC and FPGA designers

The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL

Brilliantly Radical Artificially Intelligent Neural Machine

This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, and test it on FPGA.

Final Project for Digital Systems Design Course, Fall 2020

The open-source release of "SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip"

FPGA based design

Designed as part of UCSB ECE Neuromorphic Computing Course. Includes lateral inhibition effects and unsupervised STDP learning. Classifies visual inputs '0' and '1'.

some of our simulation codes for : A Low-Cost High-Speed Neuromorphic Hardware Based on Spiking Neural Network

Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.

The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researchers under the supervision of Prof: Manan Suri (NVM &Neuromorp…

UCSB ECE594BB Instructed by Prof. Peng Li in Winter 2023

The project includes SRAM In Memory Computing Accelerator, by researchers mentioned below under the supervision of Prof: Manan Suri (NVM & Neuromorphic Hardware Research Group IIT-Delhi, https://we…

Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.

Asynchronous digital neuromorphic network build from leaky integrate and fire neurons. In the works!

Neuromorphic motor control module for FPGAs

git repository for the project "Reconfigurable Approach to Neuromorphic Hardware"

Neuromorphic Artificical Intelligence