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This is the open source tool which is used to create the System Verilog RTL code of register module

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Name		Name	Last commit message	Last commit date
Latest commit History 63 Commits
doc		doc
input		input
lib		lib
output		output
work		work
README.md		README.md

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RegRTLGen

This is the open source tool which is used to create the System Verilog RTL code of register module.

IT STILL DEVELOPING and NOT FINISHED NOW.

Folder Structure

doc : Specification documents

input : Configuration file of RegRTLGen

lib : library files

|-- rtl : RTL library

|-- python : Python library

output: RTL and document specification are created by RegRTLGen

work : Working folder contains the main script

#END

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This is the open source tool which is used to create the System Verilog RTL code of register module

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Python 95.8%
SystemVerilog 3.1%
Stata 0.5%
GAP 0.3%
Roff 0.2%
Perl 0.1%