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register-maps
register-maps PublicForked from NJDFan/register-maps
Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.
Python
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RegRTLGen
RegRTLGen PublicForked from nguyenquanicd/RegRTLGen
This is the open source tool which is used to create the System Verilog RTL code of register module
Python
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EECE490_embedded-soc
EECE490_embedded-soc PublicForked from lootr5858/EECE490_embedded-soc
Embedded SOC course with Cortex M0 & Verilog HDL
Verilog
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SweRV-FPU
SweRV-FPU PublicForked from Wishah-Naseer/SweRV-FPU
SweRV-EL2 Core with Floating Point Support
SystemVerilog
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