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This example demonstrates, how an SPI Slave can request an SPI Master to start SPI communication, so the slave can send data to the master.
❤️中国科学技术大学计算机学院课程资源(https://mbinary.xyz/ustc-cs/)
Poimandres colorscheme for Neovim written in Lua
1 min voice data can also be used to train a good TTS model! (few shot voice cloning)
Collection of Alacritty color schemes
Verilog AXI components for FPGA implementation
Code outline sidebar powered by LSP. Significantly enhanced & refactored fork of symbols-outline.nvim.
A tree like view for symbols in Neovim using the Language Server Protocol. Supports all your favourite languages.
HTTP(S)/WS(S)/TCP Tunnels to localhost using only SSH.
OpenTSN3.4开源项目的新特性：（1）交换平面深度解耦，硬件代码由TSS（时间敏感交换），HCP（硬件控制点）和OSMAC（Opensync MAC）实现。（2）集成了Opensync开源实现，支持802.1AS和AS6802两种时间同步协议；（3）集成了TSN硬件仿真工具OpenEmulator，用户可在仿真环境下运行OpenTSN3.4交换机、网卡、控制器和opensync同步软件
an opensource project to enable TSN research, including distributed and centralized version.
Time sensitive network performance evaluation toolkit, based on Zynq7000 FPGA architecture.
OpenAvnu - an Avnu sponsored repository for Time Sensitive Network (TSN and AVB) technology
Face recognition with deep neural networks.
Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
An open source library for image processing on FPGA.
Verilog Ethernet components for FPGA implementation
A test design to see how the Tri-mode Ethernet MAC can be used in a small FPGA design.