A 3-stage, 64-bit RISC-V rv64imck micro-controller.
This is a very simple 3-stage 64-bit micro-controller, implementing the
rv64imck instruction set.
It comes as a core module, and a core complex (CCX), which wraps the
core with timers, boot ROM, some RAM and other small peripherals, with
a memory port to the outside world.
Note that the K extension
is for cryptography, and is still under development.
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Required Dependencies: Yosys, Verilator, Boolector, Symbiyosys and a RISC-V Toolchain.
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Checkout the repository:
git checkout https://github.com/ben-marshall/croyde-riscv.git cd croyde-riscv/ git submodule update --init --recursive -
Setup the project workspace:
source bin/conf.sh -
Synthesise the core using Yosys Yosys.
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Verify the core using the riscv-formal framework.
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Run the RISC-V architectural compliance tests.
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Run the confidence tests set.
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Can I use this for X? - Yes you can. It's all MIT licensed.
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Should I use this for X? - Maybe. If you want a little RV64 core for your project, that is free, go for it. However, see the next bullet point.
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Has this been verified? - I have high confidence the user level ISA and instructions is correct though the riscv-formal framework. Plus the basic RISC-V architectural tests all pass, which is a basic tyre kick. I have less confidence in the priviliged architecture and interrupts implementation, or the core complex. It works for me, and my needs, but I've not done any exhaustive verification on it.
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What's the point of a 64-bit micro-controller? - If it's good enough for SiFive it's good enough for me. I wanted to implement RV64 in the simplest way possible to play around with on an cheap FPGA, which meant it had to be small to fit! More seriously, if your key workloads involve working on large variables, you might find a 64-bit core makes a lot of sense.
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What's in the name? - Nothing really. Croyde is a fantastic beach for surfing near where I grew up and there wasn't much chance of someone else picking the same name.