arch/stm32h7: add CM4 core support

arch/arm/Kconfig

@@ -468,7 +468,6 @@ config ARCH_CHIP_STM32F7
 
 config ARCH_CHIP_STM32H7
  bool "STMicro STM32 H7"
- select ARCH_CORTEXM7
  select ARCH_HAVE_MPU
  select ARCH_HAVE_I2CRESET
  select ARCH_HAVE_PROGMEM
@@ -479,11 +478,8 @@ config ARCH_CHIP_STM32H7
  select ARCH_HAVE_TICKLESS
  select ARCH_HAVE_TIMEKEEPING
  ---help---
- STMicro STM32H7 architectures (ARM Cortex-M7).
-
- BEWARE: This is a work-in-progress and not yet ready for general
- usage. See boards/arm/stm32/nucleo-h743zi/README.txt for the
- current state of the port.
+ STMicro STM32H7 architectures (ARM Cortex-M7 or
+ dual ARM Cortex-M7 Cortex-M4).
 
 config ARCH_CHIP_STM32L4
  bool "STMicro STM32 L4"

arch/arm/include/stm32h7/irq.h

@@ -72,7 +72,11 @@
 #elif defined(CONFIG_STM32H7_STM32H7B3XX)
 # include <arch/stm32h7/stm32h7x3xx_irq.h>
 #elif defined(CONFIG_STM32H7_STM32H7X5XX)
-# include <arch/stm32h7/stm32h7x5xx_irq.h>
+# if CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
+# include <arch/stm32h7/stm32h7x5xx_irq.h>
+# else
+# include <arch/stm32h7/stm32h7x5xx_cpu2_irq.h>
+# endif
 #elif defined(CONFIG_STM32H7_STM32H7X7XX)
 # include <arch/stm32h7/stm32h7x7xx_irq.h>
 #else

arch/arm/include/stm32h7/stm32h7x5xx_irq.h

@@ -116,7 +116,7 @@
 #define STM32_IRQ_ETH (STM32_IRQ_FIRST + 61) /* 61: Ethernet global interrupt */
 #define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST + 62) /* 62: Ethernet wakeup through EXTI line interrupt */
 #define STM32_IRQ_FDCANCAL (STM32_IRQ_FIRST + 63) /* 63: CAN2TX interrupts */
-#define STM32_IRQ_RESERVED64 (STM32_IRQ_FIRST + 64) /* 64: Reserved */
+#define STM32_IRQ_CM7SEND  (STM32_IRQ_FIRST + 64) /* 64: Cortex-M7 Send event interrupt */
 #define STM32_IRQ_RESERVED65 (STM32_IRQ_FIRST + 65) /* 65: Reserved */
 #define STM32_IRQ_RESERVED66 (STM32_IRQ_FIRST + 66) /* 66: Reserved */
 #define STM32_IRQ_RESERVED67 (STM32_IRQ_FIRST + 67) /* 67: Reserved */
@@ -176,9 +176,9 @@
 #define STM32_IRQ_MDIOS (STM32_IRQ_FIRST + 120) /* 120: MDIOS global interrupt */
 #define STM32_IRQ_JPEG (STM32_IRQ_FIRST + 121) /* 121: JPEG global interrupt */
 #define STM32_IRQ_MDMA (STM32_IRQ_FIRST + 122) /* 122: MDMA */
-#define STM32_IRQ_RESERVED123 (STM32_IRQ_FIRST + 123) /* 123: Reserved */
+#define STM32_IRQ_JPEG (STM32_IRQ_FIRST + 123) /* 123: JPEG */
 #define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST + 124) /* 124: SDMMC2 global interrupt */
-#define STM32_IRQ_HSEM0 (STM32_IRQ_FIRST + 125) /* 125: HSEM global interrupt 1 */
+#define STM32_IRQ_HSEM0 (STM32_IRQ_FIRST + 125) /* 125: HSEM global interrupt 0 */
 #define STM32_IRQ_RESERVED126 (STM32_IRQ_FIRST + 126) /* 126: Reserved */
 #define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 127) /* 127: ADC3 global interrupt */
 #define STM32_IRQ_DMAMUX2OVR (STM32_IRQ_FIRST + 128) /* 128: DMAMUX2 overrun interrupt */
@@ -196,12 +196,12 @@
 #define STM32_IRQ_LPTIM4 (STM32_IRQ_FIRST + 140) /* 140: LPTIM2 timer interrupt */
 #define STM32_IRQ_LPTIM5 (STM32_IRQ_FIRST + 141) /* 141: LPTIM2 timer interrupt */
 #define STM32_IRQ_LPUART (STM32_IRQ_FIRST + 142) /* 142: LPUART global interrupt */
-#define STM32_IRQ_WWDG1RST (STM32_IRQ_FIRST + 143) /* 143: Window Watchdog interrupt */
+#define STM32_IRQ_WWDG2RST (STM32_IRQ_FIRST + 143) /* 143: Window Watchdog 2 interrupt */
 #define STM32_IRQ_CRS (STM32_IRQ_FIRST + 144) /* 144: Clock Recovery System global interrupt */
-#define STM32_IRQ_RESERVED145 (STM32_IRQ_FIRST + 145) /* 145: Reserved */
+#define STM32_IRQ_ECC (STM32_IRQ_FIRST + 145) /* 145: ECC */
 #define STM32_IRQ_SAI4 (STM32_IRQ_FIRST + 146) /* 146: SAI4 global interrupt */
 #define STM32_IRQ_RESERVED147 (STM32_IRQ_FIRST + 147) /* 147: Reserved */
-#define STM32_IRQ_RESERVED148 (STM32_IRQ_FIRST + 148) /* 148: Reserved */
+#define STM32_IRQ_HOLDCORE (STM32_IRQ_FIRST + 148) /* CPUx hold */
 #define STM32_IRQ_WKUP (STM32_IRQ_FIRST + 149) /* 149: WKUP1 to WKUP6 pins */
 
 #define STM32_IRQ_NEXTINTS 150

arch/arm/src/stm32h7/CMakeLists.txt

@@ -31,13 +31,24 @@ list(
  stm32_rcc.c
  stm32_lowputc.c
  stm32_serial.c
- stm32_uid.c
-)
+ stm32_uid.c)
 
 if(CONFIG_STM32H7_PROGMEM)
  list(APPEND SRCS stm32_flash.c)
 endif()
 
+if(CONFIG_ARCH_STM32H7_DUALCORE)
+ list(APPEND SRCS stm32_dualcore.c)
+endif()
+
+if(CONFIG_STM32H7_HSEM)
+ list(APPEND SRCS stm32_hsem.c)
+endif()
+
+if(CONFIG_RPTUN)
+ list(APPEND SRCS stm32_rptun.c)
+endif()
+
 if(CONFIG_SCHED_TICKLESS)
  list(APPEND SRCS stm32_tickless.c)
 else()
@@ -48,8 +59,12 @@ if(CONFIG_STM32H7_ONESHOT)
  list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c)
 endif()
 
+if(CONFIG_ARM_MPU)
+ list(APPEND SRCS stm32_mpuinit.c)
+endif()
+
 if(CONFIG_BUILD_PROTECTED)
- list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c)
+ list(APPEND SRCS stm32_userspace.c)
 endif()
 
 if(CONFIG_ARMV7M_DTCM)

arch/arm/src/stm32h7/Kconfig

@@ -148,7 +148,7 @@ config ARCH_CHIP_STM32H745BG
  select STM32H7_FLASH_CONFIG_G
  select STM32H7_IO_CONFIG_B
  ---help---
- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM,
  LQFP208
 
 config ARCH_CHIP_STM32H745BI
@@ -157,7 +157,7 @@ config ARCH_CHIP_STM32H745BI
  select STM32H7_FLASH_CONFIG_I
  select STM32H7_IO_CONFIG_B
  ---help---
- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM,
  LQFP208
 
 config ARCH_CHIP_STM32H745IG
@@ -166,7 +166,7 @@ config ARCH_CHIP_STM32H745IG
  select STM32H7_FLASH_CONFIG_G
  select STM32H7_IO_CONFIG_I
  ---help---
- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM,
  LQFP176 or UFBGA176
 
 config ARCH_CHIP_STM32H745II
@@ -175,7 +175,7 @@ config ARCH_CHIP_STM32H745II
  select STM32H7_FLASH_CONFIG_I
  select STM32H7_IO_CONFIG_I
  ---help---
- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM,
  LQFP176 or UFBGA176
 
 config ARCH_CHIP_STM32H745XG
@@ -184,7 +184,7 @@ config ARCH_CHIP_STM32H745XG
  select STM32H7_FLASH_CONFIG_G
  select STM32H7_IO_CONFIG_X
  ---help---
- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM,
  TFBGA240
 
 config ARCH_CHIP_STM32H745XI
@@ -193,7 +193,7 @@ config ARCH_CHIP_STM32H745XI
  select STM32H7_FLASH_CONFIG_I
  select STM32H7_IO_CONFIG_X
  ---help---
- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM,
  TFBGA240
 
 config ARCH_CHIP_STM32H745ZG
@@ -202,7 +202,7 @@ config ARCH_CHIP_STM32H745ZG
  select STM32H7_FLASH_CONFIG_G
  select STM32H7_IO_CONFIG_Z
  ---help---
- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM,
  LQFP144
 
 config ARCH_CHIP_STM32H745ZI
@@ -211,7 +211,7 @@ config ARCH_CHIP_STM32H745ZI
  select STM32H7_FLASH_CONFIG_I
  select STM32H7_IO_CONFIG_Z
  ---help---
- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM,
  LQFP144
 
 config ARCH_CHIP_STM32H747XI
@@ -339,15 +339,36 @@ config STM32H7_IO_CONFIG_Z
  bool
  default n
 
-config STM32H7_STM32H7X3XX
+config ARCH_STM32H7_DUALCORE
  bool
  default n
- select ARCH_HAVE_FPU
- select ARCH_HAVE_DPFPU
+ select STM32H7_HSEM if !STM32H7_CORTEXM4_DISABLED
+ select STM32H7_HAVE_CM4
+
+choice
+ prompt "STM32 H7 Core selection"
+ default ARCH_CHIP_STM32H7_CORTEXM7
+
+config ARCH_CHIP_STM32H7_CORTEXM7
+ bool "STM32H7 Cortex-M7 core"
+ select ARCH_CORTEXM7
  select ARMV7M_HAVE_ICACHE
  select ARMV7M_HAVE_DCACHE
  select ARMV7M_HAVE_ITCM
  select ARMV7M_HAVE_DTCM
+
+config ARCH_CHIP_STM32H7_CORTEXM4
+ bool "STM32H7 Cortex-M4 core"
+ depends on ARCH_STM32H7_DUALCORE
+ select ARCH_CORTEXM4
+
+endchoice # STM32 H7 Core selection
+
+config STM32H7_STM32H7X3XX
+ bool
+ default n
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_DPFPU
  select STM32H7_HAVE_LTDC
  select STM32H7_HAVE_ETHERNET
  select STM32H7_HAVE_FMC
@@ -362,10 +383,6 @@ config STM32H7_STM32H7B3XX
  default n
  select ARCH_HAVE_FPU
  select ARCH_HAVE_DPFPU
- select ARMV7M_HAVE_ICACHE
- select ARMV7M_HAVE_DCACHE
- select ARMV7M_HAVE_ITCM
- select ARMV7M_HAVE_DTCM
  select STM32H7_HAVE_ETHERNET
  select STM32H7_HAVE_FMC
  select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V
@@ -377,12 +394,9 @@ config STM32H7_STM32H7B3XX
 config STM32H7_STM32H7X5XX
  bool
  default n
+ select ARCH_STM32H7_DUALCORE
  select ARCH_HAVE_FPU
  select ARCH_HAVE_DPFPU
- select ARMV7M_HAVE_ICACHE
- select ARMV7M_HAVE_DCACHE
- select ARMV7M_HAVE_ITCM
- select ARMV7M_HAVE_DTCM
  select STM32H7_HAVE_LTDC
  select STM32H7_HAVE_ETHERNET
  select STM32H7_HAVE_FMC
@@ -391,16 +405,14 @@ config STM32H7_STM32H7X5XX
  select STM32H7_HAVE_SPI4
  select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V
  select STM32H7_HAVE_SPI6
+ select STM32H7_HAVE_SMPS
 
 config STM32H7_STM32H7X7XX
  bool
  default n
+ select ARCH_STM32H7_DUALCORE
  select ARCH_HAVE_FPU
  select ARCH_HAVE_DPFPU
- select ARMV7M_HAVE_ICACHE
- select ARMV7M_HAVE_DCACHE
- select ARMV7M_HAVE_ITCM
- select ARMV7M_HAVE_DTCM
  select STM32H7_HAVE_LTDC
  select STM32H7_HAVE_ETHERNET
  select STM32H7_HAVE_FMC
@@ -492,6 +504,39 @@ config STM32H7_AXI_SRAM_CORRUPTION_WAR
  AXI_TARG7_FN_MOD register. This will reduce the read issuing capability
  of the SRAM to 1 at AXI interconnect level and avoid data corruption.
 
+if ARCH_STM32H7_DUALCORE
+
+if ARCH_CHIP_STM32H7_CORTEXM7
+
+config STM32H7_CORTEXM4_ENABLED
+ bool "Enable support for M4 core"
+ default y
+
+config STM32H7_CORTEXM7_BOOTM4
+ bool "Boot M4 core"
+ select STM32H7_SYSCFG
+ default y if STM32H7_CORTEXM4_ENABLED
+ default n
+
+endif
+
+config STM32H7_CORTEXM7_FLASH_SIZE
+ int "Flash reserved for M7 core"
+ default 1048576 if STM32H7_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4
+ default 2097152
+
+config STM32H7_CORTEXM7_SHMEM
+ bool
+ select ARM_MPU if ARCH_CHIP_STM32H7_CORTEXM7
+ default y if STM32H7_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4
+ default n
+
+config STM32H7_SHMEM_SRAM3
+ bool "Use SRAM3 as shared memory"
+ depends on STM32H7_CORTEXM7_SHMEM
+ default y
+
+endif
 
 config STM32_HAVE_OTA_PARTITION
  bool
@@ -538,6 +583,10 @@ menu "STM32H7 Peripheral Selection"
 # These "hidden" settings determine whether a peripheral option is available
 # for the selected MCU
 
+config STM32H7_HAVE_CM4
+ bool
+ default n
+
 config STM32H7_HAVE_LTDC
  bool
  default n
@@ -633,6 +682,10 @@ config STM32H7_LPTIM
  bool
  default n
 
+config STM32H7_HSEM
+ bool "Hardware semaphore"
+ default n
+
 config STM32H7_RTC
  bool "RTC"
  default n
@@ -2086,6 +2139,15 @@ config STM32H7_QSPI_REGDEBUG
 
 endmenu
 
+config STM32H7_BYPASS_CLOCKCONFIG
+ bool "Bypass clock configuration"
+ depends on ARCH_STM32H7_DUALCORE
+ default n if ARCH_CHIP_STM32H7_CORTEXM7
+ default y if ARCH_CHIP_STM32H7_CORTEXM4
+ ---help---
+ Bypass clock configuration. For dual core chips only one core
+ should configure clocks
+
 config STM32H7_CUSTOM_CLOCKCONFIG
  bool "Custom clock configuration"
  default n
@@ -2094,6 +2156,7 @@ config STM32H7_CUSTOM_CLOCKCONFIG
 
 config STM32H7_SRAM4EXCLUDE
  bool "Exclude SRAM4 from the heap"
+ default y if RPTUN
  default n
  ---help---
  Exclude SRAM4 from the HEAP in order to use this 64 KB region

arch/arm/src/stm32h7/Make.defs

@@ -29,6 +29,18 @@ ifeq ($(CONFIG_STM32H7_PROGMEM),y)
 CHIP_CSRCS += stm32_flash.c
 endif
 
+ifeq ($(CONFIG_ARCH_STM32H7_DUALCORE),y)
+CHIP_CSRCS += stm32_dualcore.c
+endif
+
+ifeq ($(CONFIG_STM32H7_HSEM),y)
+CHIP_CSRCS += stm32_hsem.c
+endif
+
+ifeq ($(CONFIG_RPTUN),y)
+CHIP_CSRCS += stm32_rptun.c
+endif
+
 # Required STM32H7 files
 
 CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c stm32_irq.c
@@ -45,8 +57,12 @@ ifeq ($(CONFIG_STM32H7_ONESHOT),y)
 CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c
 endif
 
+ifeq ($(CONFIG_ARM_MPU),y)
+CHIP_CSRCS += stm32_mpuinit.c
+endif
+
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c
+CHIP_CSRCS += stm32_userspace.c
 endif
 
 ifeq ($(CONFIG_ARMV7M_DTCM),y)