arch/stm32h7: add CM4 core support

arch/arm/Kconfig

@@ -468,7 +468,6 @@ config ARCH_CHIP_STM32F7
 
 config ARCH_CHIP_STM32H7
  bool "STMicro STM32 H7"
- select ARCH_CORTEXM7
  select ARCH_HAVE_MPU
  select ARCH_HAVE_I2CRESET
  select ARCH_HAVE_PROGMEM
@@ -479,11 +478,8 @@ config ARCH_CHIP_STM32H7
  select ARCH_HAVE_TICKLESS
  select ARCH_HAVE_TIMEKEEPING
  ---help---
- STMicro STM32H7 architectures (ARM Cortex-M7).
-
- BEWARE: This is a work-in-progress and not yet ready for general
- usage. See boards/arm/stm32/nucleo-h743zi/README.txt for the
- current state of the port.
+ STMicro STM32H7 architectures (ARM Cortex-M7 or
+ dual ARM Cortex-M7 Cortex-M4).
 
 config ARCH_CHIP_STM32L4
  bool "STMicro STM32 L4"

arch/arm/include/stm32h7/irq.h

@@ -72,7 +72,11 @@
 #elif defined(CONFIG_STM32H7_STM32H7B3XX)
 # include <arch/stm32h7/stm32h7x3xx_irq.h>
 #elif defined(CONFIG_STM32H7_STM32H7X5XX)
-# include <arch/stm32h7/stm32h7x5xx_irq.h>
+# if CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
+# include <arch/stm32h7/stm32h7x5xx_irq.h>
+# else
+# include <arch/stm32h7/stm32h7x5xx_cpu2_irq.h>
+# endif
 #elif defined(CONFIG_STM32H7_STM32H7X7XX)
 # include <arch/stm32h7/stm32h7x7xx_irq.h>
 #else

arch/arm/include/stm32h7/stm32h7x5xx_irq.h

@@ -116,7 +116,7 @@
 #define STM32_IRQ_ETH (STM32_IRQ_FIRST + 61) /* 61: Ethernet global interrupt */
 #define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST + 62) /* 62: Ethernet wakeup through EXTI line interrupt */
 #define STM32_IRQ_FDCANCAL (STM32_IRQ_FIRST + 63) /* 63: CAN2TX interrupts */
-#define STM32_IRQ_RESERVED64 (STM32_IRQ_FIRST + 64) /* 64: Reserved */
+#define STM32_IRQ_CM7SEND  (STM32_IRQ_FIRST + 64) /* 64: Cortex-M7 Send event interrupt */
 #define STM32_IRQ_RESERVED65 (STM32_IRQ_FIRST + 65) /* 65: Reserved */
 #define STM32_IRQ_RESERVED66 (STM32_IRQ_FIRST + 66) /* 66: Reserved */
 #define STM32_IRQ_RESERVED67 (STM32_IRQ_FIRST + 67) /* 67: Reserved */
@@ -176,9 +176,9 @@
 #define STM32_IRQ_MDIOS (STM32_IRQ_FIRST + 120) /* 120: MDIOS global interrupt */
 #define STM32_IRQ_JPEG (STM32_IRQ_FIRST + 121) /* 121: JPEG global interrupt */
 #define STM32_IRQ_MDMA (STM32_IRQ_FIRST + 122) /* 122: MDMA */
-#define STM32_IRQ_RESERVED123 (STM32_IRQ_FIRST + 123) /* 123: Reserved */
+#define STM32_IRQ_JPEG (STM32_IRQ_FIRST + 123) /* 123: JPEG */
 #define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST + 124) /* 124: SDMMC2 global interrupt */
-#define STM32_IRQ_HSEM0 (STM32_IRQ_FIRST + 125) /* 125: HSEM global interrupt 1 */
+#define STM32_IRQ_HSEM0 (STM32_IRQ_FIRST + 125) /* 125: HSEM global interrupt 0 */
 #define STM32_IRQ_RESERVED126 (STM32_IRQ_FIRST + 126) /* 126: Reserved */
 #define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 127) /* 127: ADC3 global interrupt */
 #define STM32_IRQ_DMAMUX2OVR (STM32_IRQ_FIRST + 128) /* 128: DMAMUX2 overrun interrupt */
@@ -196,12 +196,12 @@
 #define STM32_IRQ_LPTIM4 (STM32_IRQ_FIRST + 140) /* 140: LPTIM2 timer interrupt */
 #define STM32_IRQ_LPTIM5 (STM32_IRQ_FIRST + 141) /* 141: LPTIM2 timer interrupt */
 #define STM32_IRQ_LPUART (STM32_IRQ_FIRST + 142) /* 142: LPUART global interrupt */
-#define STM32_IRQ_WWDG1RST (STM32_IRQ_FIRST + 143) /* 143: Window Watchdog interrupt */
+#define STM32_IRQ_WWDG2RST (STM32_IRQ_FIRST + 143) /* 143: Window Watchdog 2 interrupt */
 #define STM32_IRQ_CRS (STM32_IRQ_FIRST + 144) /* 144: Clock Recovery System global interrupt */
-#define STM32_IRQ_RESERVED145 (STM32_IRQ_FIRST + 145) /* 145: Reserved */
+#define STM32_IRQ_ECC (STM32_IRQ_FIRST + 145) /* 145: ECC */
 #define STM32_IRQ_SAI4 (STM32_IRQ_FIRST + 146) /* 146: SAI4 global interrupt */
 #define STM32_IRQ_RESERVED147 (STM32_IRQ_FIRST + 147) /* 147: Reserved */
-#define STM32_IRQ_RESERVED148 (STM32_IRQ_FIRST + 148) /* 148: Reserved */
+#define STM32_IRQ_HOLDCORE (STM32_IRQ_FIRST + 148) /* CPUx hold */
 #define STM32_IRQ_WKUP (STM32_IRQ_FIRST + 149) /* 149: WKUP1 to WKUP6 pins */
 
 #define STM32_IRQ_NEXTINTS 150

arch/arm/src/stm32h7/CMakeLists.txt

@@ -37,6 +37,10 @@ if(CONFIG_STM32H7_PROGMEM)
  list(APPEND SRCS stm32_flash.c)
 endif()
 
+if(CONFIG_ARCH_STM32H7_DUALCORE)
+ list(APPEND SRCS stm32_dualcore.c)
+endif()
+
 if(CONFIG_STM32H7_HSEM)
  list(APPEND SRCS stm32_hsem.c)
 endif()

arch/arm/src/stm32h7/Kconfig

@@ -148,7 +148,7 @@ config ARCH_CHIP_STM32H745BG
  select STM32H7_FLASH_CONFIG_G
  select STM32H7_IO_CONFIG_B
  ---help---
- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM,
  LQFP208
 
 config ARCH_CHIP_STM32H745BI
@@ -157,7 +157,7 @@ config ARCH_CHIP_STM32H745BI
  select STM32H7_FLASH_CONFIG_I
  select STM32H7_IO_CONFIG_B
  ---help---
- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM,
  LQFP208
 
 config ARCH_CHIP_STM32H745IG
@@ -166,7 +166,7 @@ config ARCH_CHIP_STM32H745IG
  select STM32H7_FLASH_CONFIG_G
  select STM32H7_IO_CONFIG_I
  ---help---
- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM,
  LQFP176 or UFBGA176
 
 config ARCH_CHIP_STM32H745II
@@ -175,7 +175,7 @@ config ARCH_CHIP_STM32H745II
  select STM32H7_FLASH_CONFIG_I
  select STM32H7_IO_CONFIG_I
  ---help---
- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM,
  LQFP176 or UFBGA176
 
 config ARCH_CHIP_STM32H745XG
@@ -184,7 +184,7 @@ config ARCH_CHIP_STM32H745XG
  select STM32H7_FLASH_CONFIG_G
  select STM32H7_IO_CONFIG_X
  ---help---
- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM,
  TFBGA240
 
 config ARCH_CHIP_STM32H745XI
@@ -193,7 +193,7 @@ config ARCH_CHIP_STM32H745XI
  select STM32H7_FLASH_CONFIG_I
  select STM32H7_IO_CONFIG_X
  ---help---
- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM,
  TFBGA240
 
 config ARCH_CHIP_STM32H745ZG
@@ -202,7 +202,7 @@ config ARCH_CHIP_STM32H745ZG
  select STM32H7_FLASH_CONFIG_G
  select STM32H7_IO_CONFIG_Z
  ---help---
- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM,
  LQFP144
 
 config ARCH_CHIP_STM32H745ZI
@@ -211,7 +211,7 @@ config ARCH_CHIP_STM32H745ZI
  select STM32H7_FLASH_CONFIG_I
  select STM32H7_IO_CONFIG_Z
  ---help---
- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
+ Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM,
  LQFP144
 
 config ARCH_CHIP_STM32H747XI
@@ -339,15 +339,36 @@ config STM32H7_IO_CONFIG_Z
  bool
  default n
 
-config STM32H7_STM32H7X3XX
+config ARCH_STM32H7_DUALCORE
  bool
  default n
- select ARCH_HAVE_FPU
- select ARCH_HAVE_DPFPU
+ select STM32H7_HSEM if !STM32H7_CORTEXM4_DISABLED
+ select STM32H7_HAVE_CM4
+
+choice
+ prompt "STM32 H7 Core selection"
+ default ARCH_CHIP_STM32H7_CORTEXM7
+
+config ARCH_CHIP_STM32H7_CORTEXM7
+ bool "STM32H7 Cortex-M7 core"
+ select ARCH_CORTEXM7
  select ARMV7M_HAVE_ICACHE
  select ARMV7M_HAVE_DCACHE
  select ARMV7M_HAVE_ITCM
  select ARMV7M_HAVE_DTCM
+
+config ARCH_CHIP_STM32H7_CORTEXM4
+ bool "STM32H7 Cortex-M4 core"
+ depends on ARCH_STM32H7_DUALCORE
+ select ARCH_CORTEXM4
+
+endchoice # STM32 H7 Core selection
+
+config STM32H7_STM32H7X3XX
+ bool
+ default n
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_DPFPU
  select STM32H7_HAVE_LTDC
  select STM32H7_HAVE_ETHERNET
  select STM32H7_HAVE_FMC
@@ -362,10 +383,6 @@ config STM32H7_STM32H7B3XX
  default n
  select ARCH_HAVE_FPU
  select ARCH_HAVE_DPFPU
- select ARMV7M_HAVE_ICACHE
- select ARMV7M_HAVE_DCACHE
- select ARMV7M_HAVE_ITCM
- select ARMV7M_HAVE_DTCM
  select STM32H7_HAVE_ETHERNET
  select STM32H7_HAVE_FMC
  select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V
@@ -377,12 +394,9 @@ config STM32H7_STM32H7B3XX
 config STM32H7_STM32H7X5XX
  bool
  default n
+ select ARCH_STM32H7_DUALCORE
  select ARCH_HAVE_FPU
  select ARCH_HAVE_DPFPU
- select ARMV7M_HAVE_ICACHE
- select ARMV7M_HAVE_DCACHE
- select ARMV7M_HAVE_ITCM
- select ARMV7M_HAVE_DTCM
  select STM32H7_HAVE_LTDC
  select STM32H7_HAVE_ETHERNET
  select STM32H7_HAVE_FMC
@@ -391,16 +405,14 @@ config STM32H7_STM32H7X5XX
  select STM32H7_HAVE_SPI4
  select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V
  select STM32H7_HAVE_SPI6
+ select STM32H7_HAVE_SMPS
 
 config STM32H7_STM32H7X7XX
  bool
  default n
+ select ARCH_STM32H7_DUALCORE
  select ARCH_HAVE_FPU
  select ARCH_HAVE_DPFPU
- select ARMV7M_HAVE_ICACHE
- select ARMV7M_HAVE_DCACHE
- select ARMV7M_HAVE_ITCM
- select ARMV7M_HAVE_DTCM
  select STM32H7_HAVE_LTDC
  select STM32H7_HAVE_ETHERNET
  select STM32H7_HAVE_FMC
@@ -492,6 +504,39 @@ config STM32H7_AXI_SRAM_CORRUPTION_WAR
  AXI_TARG7_FN_MOD register. This will reduce the read issuing capability
  of the SRAM to 1 at AXI interconnect level and avoid data corruption.
 
+if ARCH_STM32H7_DUALCORE
+
+if ARCH_CHIP_STM32H7_CORTEXM7
+
+config STM32H7_CORTEXM4_ENABLED
+ bool "Enable support for M4 core"
+ default y
+
+config STM32H7_CORTEXM7_BOOTM4
+ bool "Boot M4 core"
+ select STM32H7_SYSCFG
+ default y if STM32H7_CORTEXM4_ENABLED
+ default n
+
+endif
+
+config STM32H7_CORTEXM7_FLASH_SIZE
+ int "Flash reserved for M7 core"
+ default 1048576 if STM32_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4
+ default 2097152
+
+config STM32H7_CORTEXM7_SHMEM
+ bool
+ select ARM_MPU if ARCH_CHIP_STM32H7_CORTEXM7
+ default y if STM32H7_CORTEXM4_ENABLED
+ default n
+
+config STM32H7_SHMEM_SRAM3
+ bool "Use SRAM3 as shared memory"
+ depends on STM32H7_CORTEXM7_SHMEM
+ default y
+
+endif
 
 config STM32_HAVE_OTA_PARTITION
  bool
@@ -538,6 +583,10 @@ menu "STM32H7 Peripheral Selection"
 # These "hidden" settings determine whether a peripheral option is available
 # for the selected MCU
 
+config STM32H7_HAVE_CM4
+ bool
+ default n
+
 config STM32H7_HAVE_LTDC
  bool
  default n

arch/arm/src/stm32h7/Make.defs

@@ -29,6 +29,10 @@ ifeq ($(CONFIG_STM32H7_PROGMEM),y)
 CHIP_CSRCS += stm32_flash.c
 endif
 
+ifeq ($(CONFIG_ARCH_STM32H7_DUALCORE),y)
+CHIP_CSRCS += stm32_dualcore.c
+endif
+
 ifeq ($(CONFIG_STM32H7_HSEM),y)
 CHIP_CSRCS += stm32_hsem.c
 endif

arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h

@@ -60,10 +60,24 @@
 
 #define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2001ffff: DTCM-RAM on TCM interface */
 #define STM32_AXISRAM_BASE 0x24000000 /* 0x24000000-0x247fffff: System AXI SRAM */
-#define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x3001ffff: System SRAM1 */
-#define STM32_SRAM2_BASE 0x30020000 /* 0x30020000-0x3003ffff: System SRAM2 */
-#define STM32_SRAM3_BASE 0x3004c000 /* 0x30040000-0x30047fff: System SRAM3 */
-#define STM32_SRAM123_BASE 0x30000000 /* 0x30000000-0x30047fff: System SRAM123 */
+
+#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
+# define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x3001ffff: System SRAM1 */
+# define STM32_SRAM2_BASE 0x30020000 /* 0x30020000-0x3003ffff: System SRAM2 */
+# define STM32_SRAM3_BASE 0x30040000 /* 0x30040000-0x30047fff: System SRAM3 */
+# define STM32_SRAM123_BASE 0x30000000 /* 0x30000000-0x30047fff: System SRAM123 */
+#else
+
+/* The AHB SRAMs of the D2 domain are also aliased to an address range below
+ * 0x2000 0000 to maintain the Cortex®-M4 Harvard architecture.
+ * For details, see RM0399 section "2.4 Embedded SRAM".
+ */
+
+# define STM32_SRAM1_BASE 0x10000000 /* 0x10000000-0x1001ffff: System SRAM1 */
+# define STM32_SRAM2_BASE 0x10020000 /* 0x10020000-0x1003ffff: System SRAM2 */
+# define STM32_SRAM3_BASE 0x10040000 /* 0x10040000-0x10047fff: System SRAM3 */
+# define STM32_SRAM123_BASE 0x10000000 /* 0x10000000-0x10047fff: System SRAM123 */
+#endif
 #define STM32_SRAM4_BASE 0x38000000 /* 0x38000000-0x3800ffff: System SRAM4 */
 #define STM32_BBSRAM_BASE 0x38800000 /* 0x38800000-0x38800fff: System Backup SRAM */
 

arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h

@@ -812,6 +812,13 @@
 /* RCC Global Control register */
 
 #define RCC_GCR_WW1RSC (1 << 0) /* Bit 0: WWDG1 reset scope control */
+#ifdef CONFIG_STM32H7_HAVE_CM4
+# define RCC_GCR_WW2RSC (1 << 1) /* Bit 1: WWDG2 reset scope control */
+#endif
+#ifdef CONFIG_STM32H7_HAVE_CM4
+# define RCC_GCR_BOOT_C1 (1 << 2) /* Bit 2: Allows CPU1 to boot */
+# define RCC_GCR_BOOT_C2 (1 << 3) /* Bit 3: Allows CPU2 to boot */
+#endif
 
 /* TODO: D3 Autonomous mode register */
 

arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h

@@ -54,6 +54,9 @@
 
 #define STM32_SYSCFG_UR_OFFSET(n) (0x0300 + ((n) << 2))
 #define STM32_SYSCFG_UR0_OFFSET 0x0300 /* User register 0 */
+#ifdef CONFIG_STM32H7_HAVE_CM4
+# define STM32_SYSCFG_UR1_OFFSET 0x0304 /* User register 2 */
+#endif
 #define STM32_SYSCFG_UR2_OFFSET 0x0308 /* User register 2 */
 #define STM32_SYSCFG_UR3_OFFSET 0x030c /* User register 3 */
 #define STM32_SYSCFG_UR4_OFFSET 0x0310 /* User register 4 */
@@ -86,6 +89,27 @@
 #define STM32_SYSCFG_CCCR (STM32_SYSCFG_BASE + STM32_SYSCFG_CCCR_OFFSET)
 #define STM32_SYSCFG_PWRCR (STM32_SYSCFG_BASE + STM32_SYSCFG_PWRCR_OFFSET)
 
+#define STM32_SYSCFG_UR0 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR0_OFFSET)
+#ifdef CONFIG_STM32H7_HAVE_CM4
+# define STM32_SYSCFG_UR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR1_OFFSET)
+#endif
+#define STM32_SYSCFG_UR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR2_OFFSET)
+#define STM32_SYSCFG_UR3 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR3_OFFSET)
+#define STM32_SYSCFG_UR4 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR4_OFFSET)
+#define STM32_SYSCFG_UR5 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR5_OFFSET)
+#define STM32_SYSCFG_UR6 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR6_OFFSET)
+#define STM32_SYSCFG_UR7 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR7_OFFSET)
+#define STM32_SYSCFG_UR8 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR8_OFFSET)
+#define STM32_SYSCFG_UR9 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR9_OFFSET)
+#define STM32_SYSCFG_UR10 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR10_OFFSET)
+#define STM32_SYSCFG_UR11 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR11_OFFSET)
+#define STM32_SYSCFG_UR12 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR12_OFFSET)
+#define STM32_SYSCFG_UR13 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR13_OFFSET)
+#define STM32_SYSCFG_UR14 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR14_OFFSET)
+#define STM32_SYSCFG_UR15 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR15_OFFSET)
+#define STM32_SYSCFG_UR16 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR16_OFFSET)
+#define STM32_SYSCFG_UR17 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR17_OFFSET)
+
 /* Register Bitfield Definitions ********************************************/
 
 /* SYSCFG peripheral mode configuration register */
@@ -191,6 +215,14 @@
 /* REVISIT: Missing bitfield definitions */
 
 #define SYSCFG_UR0_
+
+/* User register 1 */
+
+#ifdef CONFIG_STM32H7_HAVE_CM4
+# define SYSCFG_UR1_BCM4 (1 << 0) /* Bit 0: Boot Cortex-M4 */
+# define SYSCFG_UR1_BCM7 (1 << 16) /* Bit 16: Boot Cortex-M7 */
+#endif
+
 #define SYSCFG_UR2_
 #define SYSCFG_UR3_
 #define SYSCFG_UR4_