HDL libraries and projects

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Must-have verilog systemverilog modules

HYDRA: a multi-core RISC-V with cryptographically useful modes of operation

DSP WishBone Compatible Cores

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

USB3 PIPE interface for Xilinx 7-Series

RISC-V Cores, SoC platforms and SoCs

GPIO IP core from opencores.

Verification IP for Watchdog

PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory techniques. Prototype on a RISC-V rocket chip system impleme…

a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog

A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)

Naïve MIPS32 SoC implementation

Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.

A Direct Memory Access Controller (DMAC) with AHB-lite bus interface

An Implementation of Intel 8259 PIC

Implementing the interrupt controller using verilog

An Interrupt Controller configurable via the APB bus.

Interrupt Controller 68k

EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)

ASIC design Projects including an APB-Slave-UART-Receiver and an AHB-Lite FIR Filter Accelerator

A directory of Western Digital’s RISC-V SweRV Cores

An APB4-based UART Controller

An 8 input interrupt controller written in Verilog.

UVM methodology

Various HDL (Verilog) IP Cores

SDRAM controller with AXI4 interface