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Complete-ASIC-Flow-of-I2C-communication-protocol Public
Forked from asmaa2001-coder/Complete-ASIC-Flow-of-I2C-communication-protocolThis is the graduation project for ASIC Subject for CND training which is about apply ASIC flow for I2C commnuication protocol
Verilog UpdatedMay 9, 2024 -
Design-and-ASIC-Implementation-of-UART Public
Forked from basemhesham/Design-and-ASIC-Implementation-of-UARTThis repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been s…
Verilog UpdatedApr 29, 2024 -
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core-v-mcu Public
Forked from openhwgroup/core-v-mcuThis is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
SystemVerilog Other UpdatedJan 18, 2024 -
PiDRAM Public
Forked from CMU-SAFARI/PiDRAMPiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory techniques. Prototype on a RISC-V rocket chip system impleme…
UpdatedDec 11, 2023 -
verilog-axi Public
Forked from alexforencich/verilog-axiVerilog AXI components for FPGA implementation
Verilog MIT License UpdatedDec 7, 2023 -
uvm_verification_ahb_apb_bridge Public
Forked from Ismail821/uvm_verification_ahb_apb_bridgeUVM Verification enviroinment for AHB to APB bridge. Supports upto 8 APB slave Devices.
SystemVerilog UpdatedNov 2, 2023 -
UVM-Verification-of-AXI4-Lite-Interface- Public
Forked from yassinelkashef/UVM-Verification-of-AXI4-Lite-Interface-UVM Verification of AXI4-Lite Interface
Verilog UpdatedOct 26, 2023 -
IP_timer Public
Forked from efabless/EF_TCC32A 32-bit Timer/Counter/Capture Soft IP (Verilog)
Verilog MIT License UpdatedOct 24, 2023 -
SPI_Serial_Peripheral_Interface_Verilog_Modules Public
Forked from daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_ModulesImplementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
Verilog GNU General Public License v3.0 UpdatedOct 20, 2023 -
Verification_of_I2C_Protocol_IP Public
Forked from mohammedabdulhaq/Verification_of_I2C_Protocol_IPSystemVerilog UpdatedSep 17, 2023 -
I2C_Bus Public
Forked from A7med3id10/I2C_BusI2C_Bus Design and Verification
SystemVerilog UpdatedSep 14, 2023 -
axi_systemverilog Public
Forked from pulp-platform/axiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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AMBA-BUS-PROTOCOL Public
Forked from amrkhalid-star902/AMBA-BUS-PROTOCOLIn this project different bus architectures : APB , AHP , AXI that are part of AMBA (Advanced Microcontroller Bus Architecture) are implemented
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APB-Protocol-Verification-using-UVM Public
Forked from PRADEEPCHANGAL/APB-Protocol-Verification-using-UVMAPB verification using UVM
SystemVerilog UpdatedAug 21, 2023 -
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Verification-of-UART-core-using-UVM Public
Forked from Youssefmdany/Verification-of-UART-core-using-UVMVerification of UART core using UVM
SystemVerilog UpdatedJul 25, 2023 -
UVM Public
Forked from PacoReinaCampo/UVMStandard Universal Verification Methodology
SystemVerilog Apache License 2.0 UpdatedJul 14, 2023 -
my-verilog-examples Public
Forked from JeffDeCola/my-verilog-examplesA place to keep my synthesizable verilog examples.
Verilog MIT License UpdatedJul 10, 2023 -
Verilog-Design-Examples Public
Forked from snbk001/Verilog-Design-ExamplesVerilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…
Verilog UpdatedJun 29, 2023 -
ASIC-Design-Roadmap Public
Forked from abdelazeem201/ASIC-Design-RoadmapThe journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end produ…
Verilog MIT License UpdatedMay 30, 2023 -
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Sequential-Logic-Circuits Public
Forked from AlPrime2k1/Sequential-Logic-CircuitsVerilog design and testbench files for Flip Flop, Counters, RAM, FIFO, Shift Registers and other sequential logic circuits
Verilog BSD 3-Clause "New" or "Revised" License UpdatedMay 21, 2023 -
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Design-and-Simulation-of-a-32-bit-RISC-V-Core-and-APB Public
Forked from munim-sah75/Design-and-Simulation-of-a-32-bit-RISC-V-Core-and-APBA 32 Bit RISCV Core with APB protocol for data transfer written with SystemVerilog and verilog.
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ahb3lite_timer Public
Forked from RoaLogic/ahb3lite_timerRISC-V compliant Timer IP
SystemVerilog Other UpdatedMar 7, 2023