Update AXI_Master.v

anhducdinh · Aug 24, 2023 · 9ac8b31 · 9ac8b31
1 parent 67dd606
commit 9ac8b31
Showing 1 changed file with 7 additions and 5 deletions.
diff --git a/AXI/AXI_Master.v b/AXI/AXI_Master.v
@@ -1,6 +1,7 @@
-
 `timescale 1ns / 1ps
 
+
+
 module AXI_Master#(
 
 parameter DATAW = 32, 
@@ -33,8 +34,8 @@ parameter MEMSIZE = 4096
  output reg WVALID,
 
  //Signals of the Write Response channel
- input   BID,
- input   BRESP,
+ input [(DATAW/8)-1 : 0] BID,
+ input [SIZE-2 : 0] BRESP,
  input BVALID,
  output reg BREADY,
 
@@ -51,7 +52,7 @@ parameter MEMSIZE = 4096
  //Signals of the Read Data channels
  output reg [(DATAW/8)-1 : 0] RID,
  input [DATAW-1 : 0] RDATA,
- input   RRESP,
+ input [SIZE-2 : 0] RRESP,
  input RLAST,
  input RVALID,
  output reg RREADY,
@@ -1030,7 +1031,8 @@ parameter MEMSIZE = 4096
  endcase
 
  end
-
+
+
 endmodule