fixup! [TableGen] Support modelInaccessibleMemThroughRegs property fo…

…r TableGen.
Xilinx · Jul 29, 2024 · 93791d8 · 93791d8
1 parent 741e45d
commit 93791d8
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/llvm/test/TableGen/GlobalISelEmitterInaccessibleMem.td b/llvm/test/TableGen/GlobalISelEmitterInaccessibleMem.td
@@ -24,7 +24,7 @@ def : Pat<(int_intr_1 GPR32:$src),
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
-// CHECK-NEXT: // (intrinsic_w_chain:{ *:[i32] } 180:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src) => (NOP:{ *:[i32] } GPR32:{ *:[i32] }:$src)
+// CHECK-NEXT: // (intrinsic_w_chain:{ *:[i32] } 185:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src) => (NOP:{ *:[i32] } GPR32:{ *:[i32] }:$src)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::NOP),
 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src