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Insights: Xilinx/llvm-aie
Overview
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0 Active issues
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- 2 Merged pull requests
- 3 Open pull requests
- 0 Closed issues
- 0 New issues
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2 Pull requests merged by 2 people
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fixup! [MachinePipeliner] No default SwpMaxStages
#235 merged
Nov 14, 2024 -
[AIE2] Use OR to mimic MOV when copying GPR to GPR
#221 merged
Nov 11, 2024
3 Pull requests opened by 2 people
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[AIEX] Shift G_CONCAT_VECTORS closer to the user
#234 opened
Nov 11, 2024 -
Interleave loop pre-header with SWP prologue
#236 opened
Nov 14, 2024 -
[AIEX] Simplify AIEClusterBaseAddress pass
#237 opened
Nov 15, 2024
5 Unresolved conversations
Sometimes conversations happen on old items that aren’t yet closed. Here is a list of all the Issues and Pull Requests with unresolved conversations.
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Convert Loop Metadata to Asserts to help Loop rotation
#227 commented on
Nov 15, 2024 • 40 new comments -
Support for allowing direct VEXTRACT to 20-bit registers
#233 commented on
Nov 15, 2024 • 10 new comments -
[AIEX] Delay metalizing of multi-slot until iterative scheduling is converged
#182 commented on
Nov 14, 2024 • 4 new comments -
[AIEX] Ignore bank conflict if in the next cycle we cannot schedule the instruction.
#229 commented on
Nov 11, 2024 • 1 new comment -
[AIEX] Reschedule multi-slot instruction for better packing/schedule
#217 commented on
Nov 11, 2024 • 0 new comments