[AIE2] Lowering of natively unsupported SEXT_INREGs

We can lower before instruction selection. As we select SEXT_INREG using shifts for size > 16, we can have some shift optimization opportunities.
Xilinx · Jul 23, 2024 · 13fbd6a · 13fbd6a
1 parent 7549810
commit 13fbd6a
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Showing 17 changed files with 289 additions and 147 deletions.
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -408,6 +408,7 @@ class LegalizerHelper {
  LegalizeResult lowerFFloor(MachineInstr &MI);
  LegalizeResult lowerMergeValues(MachineInstr &MI);
  LegalizeResult lowerUnmergeValues(MachineInstr &MI);
+ LegalizeResult lowerSextInreg(MachineInstr &MI);
  LegalizeResult lowerExtractInsertVectorElt(MachineInstr &MI);
  LegalizeResult lowerShuffleVector(MachineInstr &MI);
  Register getDynStackAllocTargetPtr(Register SPReg, Register AllocSize,

diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3866,20 +3866,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
  return lowerMergeValues(MI);
  case G_UNMERGE_VALUES:
  return lowerUnmergeValues(MI);
- case TargetOpcode::G_SEXT_INREG: {
- assert(MI.getOperand(2).isImm() && "Expected immediate");
- int64_t SizeInBits = MI.getOperand(2).getImm();
-
- auto [DstReg, SrcReg] = MI.getFirst2Regs();
- LLT DstTy = MRI.getType(DstReg);
- Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
-
- auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
- MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0));
- MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0));
- MI.eraseFromParent();
- return Legalized;
- }
+ case TargetOpcode::G_SEXT_INREG:
+ return lowerSextInreg(MI);
  case G_EXTRACT_VECTOR_ELT:
  case G_INSERT_VECTOR_ELT:
  return lowerExtractInsertVectorElt(MI);
@@ -7282,6 +7270,23 @@ LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
  return Legalized;
 }
 
+LegalizerHelper::LegalizeResult
+LegalizerHelper::lowerSextInreg(MachineInstr &MI) {
+ assert(MI.getOperand(2).isImm() && "Expected immediate");
+ int64_t SizeInBits = MI.getOperand(2).getImm();
+
+ auto [DstReg, SrcReg] = MI.getFirst2Regs();
+ LLT DstTy = MRI.getType(DstReg);
+ Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
+
+ auto MIBSz =
+ MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
+ MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0));
+ MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0));
+ MI.eraseFromParent();
+ return Legalized;
+}
+
 /// Lower a vector extract or insert by writing the vector to a stack temporary
 /// and reloading the element or vector.
 ///

diff --git a/llvm/lib/Target/AIE/AIE2InstructionSelector.cpp b/llvm/lib/Target/AIE/AIE2InstructionSelector.cpp
@@ -1148,20 +1148,7 @@ bool AIE2InstructionSelector::selectG_SEXT_INREG(MachineInstr &I,
  } else if (Imm == 16) {
  MI = MIB.buildInstr(AIE2::EXTENDs16, {DstReg}, {SrcReg});
  } else {
- if (Imm < 0 || Imm > 32)
- return false;
-
- // Expand sext_inreg into ashr (shl reg, amnt), amnt
- auto SHLAmount =
- MIB.buildInstr(AIE2::MOV_RLC_imm10_pseudo, {&AIE2::eRRegClass}, {})
- .addImm(32 - Imm);
- MI = MIB.buildInstr(AIE2::LSHL, {&AIE2::eRRegClass},
- {SrcReg, SHLAmount.getReg(0)});
- auto SHRAmount =
- MIB.buildInstr(AIE2::MOV_RLC_imm10_pseudo, {&AIE2::eRRegClass}, {})
- .addImm(-(32 - Imm));
- MI = MIB.buildInstr(AIE2::ASHL, {DstReg},
- {MI.getReg(0), SHRAmount.getReg(0)});
+ llvm_unreachable("Cannot handle type in selectG_SEXT_INREG");
  }
 
  I.eraseFromParent();

diff --git a/llvm/lib/Target/AIE/AIELegalizerInfo.cpp b/llvm/lib/Target/AIE/AIELegalizerInfo.cpp
@@ -255,8 +255,8 @@ AIELegalizerInfo::AIELegalizerInfo(const AIEBaseSubtarget &ST) {
  .clampScalar(0, S32, S32);
 
  getActionDefinitionsBuilder(G_SEXT_INREG)
- .legalForTypeWithAnyImm({S32})
- .lower();
+ .custom()
+ .legalForTypeWithAnyImm({S32});
 
  getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
  .legalFor({{S32, S32}})
@@ -561,6 +561,8 @@ bool AIELegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
  return legalizeG_BUILD_VECTOR(Helper, MI);
  case TargetOpcode::G_UNMERGE_VALUES:
  return legalizeG_UNMERGE_VALUES(Helper, MI);
+ case TargetOpcode::G_SEXT_INREG:
+ return legalizeG_SEXT_INREG(Helper, MI);
  }
 
  llvm_unreachable("Un-expected custom legalization");
@@ -770,6 +772,23 @@ bool AIELegalizerInfo::legalizeG_UNMERGE_VALUES(LegalizerHelper &Helper,
  return true;
 }
 
+bool AIELegalizerInfo::legalizeG_SEXT_INREG(LegalizerHelper &Helper,
+ MachineInstr &MI) const {
+
+ MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
+ MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
+
+ const Register DestReg = MI.getOperand(0).getReg();
+ const LLT DestRegTy = MRI.getType(DestReg);
+ const LLT S32 = LLT::scalar(32);
+
+ const int64_t Imm = MI.getOperand(2).getImm();
+ if ((Imm != 8 && Imm != 16) || DestRegTy != S32)
+ Helper.lowerSextInreg(MI);
+
+ return true;
+}
+
 bool AIELegalizerInfo::legalizeG_VASTART(LegalizerHelper &Helper,
  MachineInstr &MI) const {
  MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;

diff --git a/llvm/lib/Target/AIE/AIELegalizerInfo.h b/llvm/lib/Target/AIE/AIELegalizerInfo.h
@@ -37,6 +37,7 @@ class AIELegalizerInfo : public LegalizerInfo {
  bool legalizeG_BUILD_VECTOR(LegalizerHelper &Helper, MachineInstr &MI) const;
  bool legalizeG_UNMERGE_VALUES(LegalizerHelper &Helper,
  MachineInstr &MI) const;
+ bool legalizeG_SEXT_INREG(LegalizerHelper &Helper, MachineInstr &MI) const;
  bool legalizeG_VAARG(LegalizerHelper &Helper, MachineInstr &MI) const;
  bool legalizeMemCalls(LegalizerHelper &Helper, MachineInstr &MI,
  LostDebugLocObserver &LocObserver) const;

diff --git a/llvm/test/CodeGen/AIE/GlobalISel/legalize-abs.mir b/llvm/test/CodeGen/AIE/GlobalISel/legalize-abs.mir
@@ -14,10 +14,12 @@ body: |
  bb.0:
  ; CHECK-LABEL: name: abs_s1
  ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $r6
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
- ; CHECK-NEXT: [[ABS:%[0-9]+]]:_(s32) = G_ABS [[SEXT_INREG]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ABS]], [[C]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; CHECK-NEXT: [[ABS:%[0-9]+]]:_(s32) = G_ABS [[ASHR]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ABS]], [[C1]]
  ; CHECK-NEXT: $r0 = COPY [[AND]](s32)
  %0:_(s32) = COPY $r6
  %1:_(s1) = G_TRUNC %0
@@ -32,10 +34,12 @@ body: |
  bb.0:
  ; CHECK-LABEL: name: abs_s7
  ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $r6
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
- ; CHECK-NEXT: [[ABS:%[0-9]+]]:_(s32) = G_ABS [[SEXT_INREG]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ABS]], [[C]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; CHECK-NEXT: [[ABS:%[0-9]+]]:_(s32) = G_ABS [[ASHR]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ABS]], [[C1]]
  ; CHECK-NEXT: $r0 = COPY [[AND]](s32)
  %0:_(s32) = COPY $r6
  %1:_(s7) = G_TRUNC %0

diff --git a/llvm/test/CodeGen/AIE/GlobalISel/legalize-ashr.mir b/llvm/test/CodeGen/AIE/GlobalISel/legalize-ashr.mir
@@ -241,11 +241,13 @@ body: |
  ; CHECK-NEXT: {{ $}}
  ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r6
  ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r7
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; CHECK-NEXT: $r0 = COPY [[ASHR]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
+ ; CHECK-NEXT: $r0 = COPY [[ASHR1]](s32)
  %0:_(s32) = COPY $r6
  %1:_(s32) = COPY $r7
  %2:_(s7) = G_TRUNC %0
@@ -266,11 +268,13 @@ body: |
  ; CHECK-NEXT: {{ $}}
  ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r6
  ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r7
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; CHECK-NEXT: $r0 = COPY [[ASHR]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
+ ; CHECK-NEXT: $r0 = COPY [[ASHR1]](s32)
  %0:_(s32) = COPY $r6
  %1:_(s32) = COPY $r7
  %2:_(s24) = G_TRUNC %0

diff --git a/llvm/test/CodeGen/AIE/GlobalISel/legalize-ptr-add.mir b/llvm/test/CodeGen/AIE/GlobalISel/legalize-ptr-add.mir
@@ -39,9 +39,10 @@ body: |
  ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
  ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
  ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SHL]], 20
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s20) = G_TRUNC [[ASHR]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s20) = G_TRUNC [[ASHR1]](s32)
  ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[TRUNC]](s20)
  ; CHECK-NEXT: $p0 = COPY [[PTR_ADD]](p0)
  %0:_(p0) = COPY $p0
@@ -63,9 +64,11 @@ body: |
  ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
  ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
  ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SHL]], 20
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s20) = G_TRUNC [[ASHR]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[C1]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+ ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s20) = G_TRUNC [[ASHR1]](s32)
  ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[TRUNC]](s20)
  ; CHECK-NEXT: $p0 = COPY [[PTR_ADD]](p0)
  %0:_(p0) = COPY $p0

diff --git a/llvm/test/CodeGen/AIE/GlobalISel/legalize-saddo.mir b/llvm/test/CodeGen/AIE/GlobalISel/legalize-saddo.mir
@@ -45,15 +45,19 @@ body: |
  ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r7
  ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
  ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 7
- ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C1]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
+ ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
+ ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C1]](s32)
  ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR2]](s32), [[COPY2]]
  ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP1]], [[ICMP]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
  ; CHECK-NEXT: $r0 = COPY [[AND]](s32)
  ; CHECK-NEXT: $r1 = COPY [[XOR]](s32)
  %0:_(s32) = COPY $r6

diff --git a/llvm/test/CodeGen/AIE/GlobalISel/legalize-sel-sext-inreg-shift.mir b/llvm/test/CodeGen/AIE/GlobalISel/legalize-sel-sext-inreg-shift.mir
@@ -0,0 +1,127 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+#
+# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+#
+# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
+# RUN: llc -mtriple aie2 --start-before=legalizer --stop-after=instruction-select \
+# RUN: %s -verify-machineinstrs -o - | FileCheck %s
+
+
+# This test verifies different combinations of SEXT_INREG and shifts
+# against legalization and selection.
+
+---
+name: test_sext_inreg7_shift
+body: |
+ bb.0:
+ liveins: $r6
+
+ ; CHECK-LABEL: name: test_sext_inreg7_shift
+ ; CHECK: liveins: $r6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:er = COPY $r6
+ ; CHECK-NEXT: [[MOV_RLC_imm10_pseudo:%[0-9]+]]:er = MOV_RLC_imm10_pseudo 29
+ ; CHECK-NEXT: [[LSHL:%[0-9]+]]:er = LSHL [[COPY]], [[MOV_RLC_imm10_pseudo]]
+ ; CHECK-NEXT: [[MOV_RLC_imm10_pseudo1:%[0-9]+]]:er = MOV_RLC_imm10_pseudo -29
+ ; CHECK-NEXT: [[ASHL:%[0-9]+]]:er = ASHL [[LSHL]], [[MOV_RLC_imm10_pseudo1]]
+ ; CHECK-NEXT: $r0 = COPY [[ASHL]]
+ %0:_(s32) = COPY $r6
+ %1:_(s32) = G_CONSTANT i32 4
+ %2:_(s32) = G_SHL %0, %1
+ %3:_(s32) = G_SEXT_INREG %2, 7
+ %4:_(s32) = G_ASHR %3, %1
+ $r0 = COPY %4
+...
+
+---
+name: test_sext_inreg20_shift
+body: |
+ bb.0:
+ liveins: $r6
+
+ ; CHECK-LABEL: name: test_sext_inreg20_shift
+ ; CHECK: liveins: $r6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:er = COPY $r6
+ ; CHECK-NEXT: [[MOV_RLC_imm10_pseudo:%[0-9]+]]:er = MOV_RLC_imm10_pseudo 16
+ ; CHECK-NEXT: [[LSHL:%[0-9]+]]:er = LSHL [[COPY]], [[MOV_RLC_imm10_pseudo]]
+ ; CHECK-NEXT: [[MOV_RLC_imm10_pseudo1:%[0-9]+]]:er = MOV_RLC_imm10_pseudo -16
+ ; CHECK-NEXT: [[ASHL:%[0-9]+]]:er = ASHL [[LSHL]], [[MOV_RLC_imm10_pseudo1]]
+ ; CHECK-NEXT: $r0 = COPY [[ASHL]]
+ %0:_(s32) = COPY $r6
+ %1:_(s32) = G_CONSTANT i32 4
+ %2:_(s32) = G_SHL %0, %1
+ %3:_(s32) = G_SEXT_INREG %2, 20
+ %4:_(s32) = G_ASHR %3, %1
+ $r0 = COPY %4
+...
+
+---
+name: test_sext_inreg20_shift20
+body: |
+ bb.0:
+ liveins: $r6
+
+ ; CHECK-LABEL: name: test_sext_inreg20_shift20
+ ; CHECK: liveins: $r6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[MOV_RLC_imm10_pseudo:%[0-9]+]]:er = MOV_RLC_imm10_pseudo 0
+ ; CHECK-NEXT: $r0 = COPY [[MOV_RLC_imm10_pseudo]]
+ %0:_(s32) = COPY $r6
+ %1:_(s32) = G_CONSTANT i32 20
+ %2:_(s32) = G_SHL %0, %1
+ %3:_(s32) = G_SEXT_INREG %2, 20
+ %4:_(s32) = G_ASHR %3, %1
+ $r0 = COPY %4
+...
+
+---
+name: test_sext_inreg16_shift
+body: |
+ bb.0:
+ liveins: $r6
+
+ ; CHECK-LABEL: name: test_sext_inreg16_shift
+ ; CHECK: liveins: $r6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:er = COPY $r6
+ ; CHECK-NEXT: [[MOV_RLC_imm10_pseudo:%[0-9]+]]:er = MOV_RLC_imm10_pseudo 4
+ ; CHECK-NEXT: [[LSHL:%[0-9]+]]:er = LSHL [[COPY]], [[MOV_RLC_imm10_pseudo]]
+ ; CHECK-NEXT: [[EXTENDs16_:%[0-9]+]]:er = EXTENDs16 [[LSHL]]
+ ; CHECK-NEXT: [[MOV_RLC_imm10_pseudo1:%[0-9]+]]:er = MOV_RLC_imm10_pseudo -4
+ ; CHECK-NEXT: [[ASHL:%[0-9]+]]:er = ASHL [[EXTENDs16_]], [[MOV_RLC_imm10_pseudo1]]
+ ; CHECK-NEXT: $r0 = COPY [[ASHL]]
+ %0:_(s32) = COPY $r6
+ %1:_(s32) = G_CONSTANT i32 4
+ %2:_(s32) = G_SHL %0, %1
+ %3:_(s32) = G_SEXT_INREG %2, 16
+ %4:_(s32) = G_ASHR %3, %1
+ $r0 = COPY %4
+...
+
+---
+name: test_sext_inreg8_shift
+body: |
+ bb.0:
+ liveins: $r6
+
+ ; CHECK-LABEL: name: test_sext_inreg8_shift
+ ; CHECK: liveins: $r6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:er = COPY $r6
+ ; CHECK-NEXT: [[MOV_RLC_imm10_pseudo:%[0-9]+]]:er = MOV_RLC_imm10_pseudo 4
+ ; CHECK-NEXT: [[LSHL:%[0-9]+]]:er = LSHL [[COPY]], [[MOV_RLC_imm10_pseudo]]
+ ; CHECK-NEXT: [[EXTENDs8_:%[0-9]+]]:er = EXTENDs8 [[LSHL]]
+ ; CHECK-NEXT: [[MOV_RLC_imm10_pseudo1:%[0-9]+]]:er = MOV_RLC_imm10_pseudo -4
+ ; CHECK-NEXT: [[ASHL:%[0-9]+]]:er = ASHL [[EXTENDs8_]], [[MOV_RLC_imm10_pseudo1]]
+ ; CHECK-NEXT: $r0 = COPY [[ASHL]]
+ %0:_(s32) = COPY $r6
+ %1:_(s32) = G_CONSTANT i32 4
+ %2:_(s32) = G_SHL %0, %1
+ %3:_(s32) = G_SEXT_INREG %2, 8
+ %4:_(s32) = G_ASHR %3, %1
+ $r0 = COPY %4
+...
+