Documentation for NVDLA.

RTL, Cmodel, and testbench for NVDLA

NVDLA SW

SpikingJelly is an open-source deep learning framework for Spiking Neural Network (SNN) based on PyTorch.

Library of deep learning models and datasets designed to make deep learning more accessible and accelerate ML research.

为GPT/GLM等LLM大语言模型提供实用化交互接口，特别优化论文阅读/润色/写作体验，模块化设计，支持自定义快捷按钮&函数插件，支持Python和C++等项目剖析&自译解功能，PDF/LaTex论文翻译&总结功能，支持并行问询多种LLM模型，支持chatglm3等本地模型。接入通义千问, deepseekcoder, 讯飞星火, 文心一言, llama2, rwkv, claude2, m…

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first …

The Ultra-Low Power RISC-V Core

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

RISC-V CPU Core (RV32IM)

A FPGA friendly 32 bit RISC-V CPU implementation

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Simple Cowtransfer Uploader/Downloader in Golang

A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 16 (fp16).

FPGA/AES/LeNet/VGG16

The resnet20 cnn inference accelerator on cifar10 net about twn net with hls tool

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

Basic MPU6050 Arduino sketch of sensor function