-
pytorch-cifar100 Public
Forked from weiaicunzai/pytorch-cifar100Practice on cifar100(ResNet, DenseNet, VGG, GoogleNet, InceptionV3, InceptionV4, Inception-ResNetv2, Xception, Resnet In Resnet, ResNext,ShuffleNet, ShuffleNetv2, MobileNet, MobileNetv2, SqueezeNet…
Python UpdatedOct 31, 2024 -
-
mamba Public
Forked from state-spaces/mambaMamba SSM architecture
Python Apache License 2.0 UpdatedOct 13, 2024 -
2024-05-TCAS-1-Citation Public
This repo is about the citation and idea of the 2024-05 TCAS-1, which is about an ACIM design in 40nm design
UpdatedMay 1, 2024 -
sv-tutorial Public
Forked from ARC-Lab-UF/sv-tutorialSystemVerilog Tutorial
SystemVerilog GNU General Public License v3.0 UpdatedNov 29, 2023 -
spikingjelly Public
Forked from fangwei123456/spikingjellySpikingJelly is an open-source deep learning framework for Spiking Neural Network (SNN) based on PyTorch.
Python Other UpdatedOct 12, 2023 -
netlist-level hardware optimization tool based on BP
UpdatedJun 4, 2023 -
-
mindsdb Public
Forked from mindsdb/mindsdbMindsDB is a Server for Artificial Intelligence Logic. Enabling developers to ship AI powered projects to production in a fast and scalable way.
Python GNU General Public License v3.0 UpdatedJun 4, 2023 -
tensor2tensor Public
Forked from tensorflow/tensor2tensorLibrary of deep learning models and datasets designed to make deep learning more accessible and accelerate ML research.
Python Apache License 2.0 UpdatedJun 2, 2023 -
VexRiscv Public
Forked from SpinalHDL/VexRiscvA FPGA friendly 32 bit RISC-V CPU implementation
Assembly MIT License UpdatedJul 22, 2022 -
Basic-SIMD-Processor-Verilog-Tutorial Public
Forked from zslwyuan/Basic-SIMD-Processor-Verilog-TutorialImplementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first …
-
darkriscv Public
Forked from darklife/darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
C BSD 3-Clause "New" or "Revised" License UpdatedJul 9, 2022 -
RTL, Cmodel, and testbench for NVDLA
Verilog Other UpdatedMar 2, 2022 -
e203_hbirdv2 Public
Forked from riscv-mcu/e203_hbirdv2The Ultra-Low Power RISC-V Core
Verilog Apache License 2.0 UpdatedFeb 24, 2022 -
riscv Public
Forked from ultraembedded/riscvRISC-V CPU Core (RV32IM)
Verilog BSD 3-Clause "New" or "Revised" License UpdatedSep 18, 2021 -
e200_opensource Public
Forked from SI-RISCV/e200_opensourceDeprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
Verilog Apache License 2.0 UpdatedMar 24, 2021 -
-
-
ODIN Public
Forked from ChFrenkel/ODINODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.
Verilog Other UpdatedApr 20, 2019
{{ message }}