[bsp/phytium]中断相关修改 (#8742)

* update smp 4

bsp/phytium/board/board.c

@@ -21,6 +21,7 @@
 #include <mmu.h>
 #include <mm_aspace.h> /* TODO: why need application space when RT_SMART off */
 #include <mm_page.h>
+#include "phytium_interrupt.h"
 
 #ifdef RT_USING_SMART
  #include <page.h>
@@ -157,7 +158,7 @@ void rt_hw_board_aarch64_init(void)
  rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
 
- rt_hw_interrupt_init();
+ phytium_interrupt_init();
 
  rt_hw_gtimer_init();
 

bsp/phytium/board/phytium_cpu.c

@@ -20,9 +20,6 @@
 
 #include "phytium_cpu.h"
 
-
-#if defined(TARGET_ARMV8_AARCH64)
-
 /**
 @name: phytium_cpu_id_mapping
 @msg: Map Phytium CPU ID
@@ -33,7 +30,6 @@
 int phytium_cpu_id_mapping(int cpu_id)
 {
 #if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
-#if RT_CPUS_NR <= 2
  switch (cpu_id)
  {
  case 0:
@@ -52,9 +48,6 @@ int phytium_cpu_id_mapping(int cpu_id)
 #else
  return (int)cpu_id;
 #endif
-#else
- return (int)cpu_id;
-#endif
 }
 
 int rt_hw_cpu_id(void)
@@ -70,44 +63,7 @@ int rt_hw_cpu_id(void)
  return phytium_cpu_id_mapping(cpu_id);
 }
 
-#else
-
-int phytium_cpu_id_mapping(int cpu_id)
-{
-#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
- switch (cpu_id)
- {
- case 0:
- return 2;
- case 1:
- return 3;
- case 2:
- return 0;
- case 3:
- return 1;
- default:
- RT_ASSERT(0);
- return 0;
- break;
- }
-#else
- return (int)cpu_id;
-#endif
-}
-
-int rt_hw_cpu_id(void)
-{
- FError ret;
- u32 cpu_id;
- ret = GetCpuId(&cpu_id);
-
- if (ret != ERR_SUCCESS)
- {
- RT_ASSERT(0);
- }
-
- return phytium_cpu_id_mapping(cpu_id);
-}
+#if defined(TARGET_ARMV8_AARCH32)
 
 rt_uint64_t get_main_cpu_affval(void)
 {

bsp/phytium/board/phytium_cpu.h

@@ -48,24 +48,17 @@ rt_inline rt_uint32_t platform_get_gic_dist_base(void)
 /* the basic constants and interfaces needed by gic */
 rt_inline rt_uint32_t platform_get_gic_redist_base(void)
 {
-#if RT_CPUS_NR <= 2
- return GICV3_RD_BASE_ADDR + 2 * GICV3_RD_OFFSET;
-#else
- return GICV3_RD_BASE_ADDR;
-#endif
  return 0;
 }
 
 rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
 {
- return 0U; /* unused in gicv3 */
+ return 0; /* unused in gicv3 */
 }
 
 #endif
 
 
 int phytium_cpu_id_mapping(int cpu_id);
 
-
-
 #endif // !

bsp/phytium/board/secondary_cpu.c

@@ -40,6 +40,7 @@
 
 rt_uint64_t rt_cpu_mpidr_early[] =
 {
+
 #if defined(TARGET_E2000D)
  [0] = 0x80000200,
  [1] = 0x80000201,
@@ -78,7 +79,7 @@ void rt_hw_secondary_cpu_up(void)
  {
  continue;
  }
- cpu_mask = 1 << phytium_cpu_id_mapping(i);
+ cpu_mask = 1<<phytium_cpu_id_mapping(i);
 
 #if defined(TARGET_ARMV8_AARCH64)
  /* code */
@@ -103,7 +104,6 @@ void rt_hw_secondary_cpu_up(void)
  */
 extern size_t MMUTable[];
 
-
 void rt_hw_secondary_cpu_bsp_start(void)
 {
  /* spin lock init */
@@ -125,7 +125,7 @@ void rt_hw_secondary_cpu_bsp_start(void)
 #if defined(TARGET_ARMV8_AARCH64)
  arm_gic_cpu_init(0, 0);
 
- arm_gic_redist_init(0, 0);
+ phytium_aarch64_arm_gic_redist_init();
  rt_kprintf("arm_gic_redist_init is over rt_hw_cpu_id() is %d \r\n", rt_hw_cpu_id());
 #else
  arm_gic_cpu_init(0);

bsp/phytium/libraries/common/phytium_interrupt.c

@@ -0,0 +1,150 @@
+#include "rtconfig.h"
+#if defined(TARGET_ARMV8_AARCH64)
+#include <rthw.h>
+#include <rtthread.h>
+#include "interrupt.h"
+#include "gic.h"
+#include "gicv3.h"
+#include "ioremap.h"
+#include "phytium_cpu.h"
+#include "ftypes.h"
+#include "fparameters.h"
+
+struct arm_gic *phytium_gic_table;
+
+extern struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+int arm_gic_redist_address_set(rt_uint64_t index, rt_uint64_t redist_addr, int cpu_id)
+{
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ if (cpu_id == 0)
+ {
+ rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, &cpu_id, sizeof(cpu_id));
+ }
+
+ phytium_gic_table[index].redist_hw_base[cpu_id] = redist_addr;
+
+ return 0;
+}
+
+static int arm_gicv3_wait_rwp(rt_uint64_t index, rt_uint64_t irq)
+{
+ rt_uint64_t rwp_bit;
+ rt_uint64_t base;
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ if (irq < 32)
+ {
+ rt_int32_t cpu_id = rt_hw_cpu_id();
+
+ base = phytium_gic_table[index].redist_hw_base[cpu_id];
+ rwp_bit = GICR_CTLR_RWP;
+ }
+ else
+ {
+ base = phytium_gic_table[index].dist_hw_base;
+ rwp_bit = GICD_CTLR_RWP;
+ }
+
+ while (HWREG32(base) & rwp_bit)
+ {
+ }
+
+ return 0;
+}
+
+int phytium_aarch64_arm_gic_redist_init()
+{
+ rt_uint64_t cpu_id = rt_hw_cpu_id();
+ rt_uint64_t redist_base = phytium_gic_table[0].redist_hw_base[cpu_id];
+
+ /* redistributor enable */
+ GIC_RDIST_WAKER(redist_base) &= ~(1 << 1);
+ while (GIC_RDIST_WAKER(redist_base) & (1 << 2))
+ {
+ }
+
+ /* Disable all sgi and ppi interrupt */
+ GIC_RDISTSGI_ICENABLER0(redist_base) = 0xffffffff;
+ arm_gicv3_wait_rwp(0, 0);
+
+ /* Clear all inetrrupt pending */
+ GIC_RDISTSGI_ICPENDR0(redist_base) = 0xffffffff;
+
+ /* the corresponding interrupt is Group 1 or Non-secure Group 1. */
+ GIC_RDISTSGI_IGROUPR0(redist_base, 0) = 0xffffffff;
+ GIC_RDISTSGI_IGRPMODR0(redist_base, 0) = 0xffffffff;
+
+ /* Configure default priorities for SGI 0:15 and PPI 16:31. */
+ for (int i = 0; i < 32; i += 4)
+ {
+ GIC_RDISTSGI_IPRIORITYR(redist_base, i) = 0xa0a0a0a0U;
+ }
+
+ /* Trigger level for PPI interrupts*/
+ GIC_RDISTSGI_ICFGR1(redist_base) = 0;
+
+ return 0;
+}
+
+void phytium_interrupt_init(void)
+{
+ rt_uint64_t gic_cpu_base;
+ rt_uint64_t gic_dist_base;
+ rt_uint64_t gic_irq_start;
+ rt_uint64_t redist_addr;
+
+ phytium_gic_table = (struct arm_gic *)arm_gic_get_gic_table_addr();
+ /* initialize vector table */
+ rt_hw_vector_init();
+
+ /* initialize exceptions table */
+ rt_memset(isr_table, 0x00, sizeof(isr_table));
+
+#if defined(RT_USING_SMART)
+ gic_dist_base = (rt_uint64_t)rt_ioremap((void *)platform_get_gic_dist_base(), 0x40000);
+ gic_cpu_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_cpu_base(), 0x1000);
+ redist_addr = (rt_uint64_t)rt_ioremap(GICV3_RD_BASE_ADDR, 4 * GICV3_RD_OFFSET);
+#else
+ gic_dist_base = platform_get_gic_dist_base();
+ gic_cpu_base = platform_get_gic_cpu_base();
+ redist_addr = GICV3_RD_BASE_ADDR;
+#endif
+
+ gic_irq_start = 0;
+ arm_gic_dist_init(0, gic_dist_base, gic_irq_start);
+ arm_gic_cpu_init(0, gic_cpu_base);
+ arm_gic_redist_address_set(0, redist_addr + 2 * GICV3_RD_OFFSET, 0);
+
+#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
+#if RT_CPUS_NR == 2
+ arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
+#elif RT_CPUS_NR == 3
+ arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
+ arm_gic_redist_address_set(0, redist_addr, 2);
+#elif RT_CPUS_NR == 4
+ arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
+ arm_gic_redist_address_set(0, redist_addr, 2);
+ arm_gic_redist_address_set(0, redist_addr + GICV3_RD_OFFSET, 3);
+#endif
+#else
+#if defined(TARGET_E2000D)
+ rt_uint32_t cpu_offset = 2;
+#endif
+#if RT_CPUS_NR == 2
+ arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
+#elif RT_CPUS_NR == 3
+ arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
+ arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
+#elif RT_CPUS_NR == 4
+ arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
+ arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
+ arm_gic_redist_address_set(0, redist_addr + (3 + cpu_offset) * GICV3_RD_OFFSET, 3);
+#endif
+#endif
+
+ phytium_aarch64_arm_gic_redist_init();
+}
+#endif

bsp/phytium/libraries/common/phytium_interrupt.h

@@ -0,0 +1,17 @@
+#ifndef PHYTIUM_INTERRUPT_H
+#define PHYTIUM_INTERRUPT_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#include "rtconfig.h"
+#if defined(TARGET_ARMV8_AARCH64)
+void phytium_interrupt_init(void);
+
+int phytium_aarch64_arm_gic_redist_init(void);
+#endif
+#ifdef __cplusplus
+}
+#endif
+#endif

bsp/phytium/libraries/drivers/drv_can.c

@@ -166,7 +166,7 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
  struct phytium_can *drv_can;
  drv_can = (struct phytium_can *)can->parent.user_data;
  RT_ASSERT(drv_can != RT_NULL);
- rt_uint32_t cpu_id;
+ rt_uint32_t cpu_id = rt_hw_cpu_id();
  FCanIntrEventConfig intr_event;
  FError status = FT_SUCCESS;
 
@@ -177,7 +177,6 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
  switch (cmd)
  {
  case RT_DEVICE_CTRL_SET_INT:
- GetCpuId(&cpu_id);
  rt_hw_interrupt_set_target_cpus(drv_can->can_handle.config.irq_num, cpu_id);
  argval = (rt_uint32_t) arg;
  /*Open different interrupts*/

bsp/phytium/libraries/drivers/drv_gpio.c

@@ -63,10 +63,9 @@ extern FIOPadCtrl iopad_ctrl;
 /*******************************Api Functions*********************************/
 static void FGpioOpsSetupCtrlIRQ(FGpio *ctrl)
 {
- u32 cpu_id;
+ rt_uint32_t cpu_id = rt_hw_cpu_id();
  u32 irq_num = ctrl->config.irq_num[0];
 
- GetCpuId(&cpu_id);
  LOG_D("In FGpioOpsSetupCtrlIRQ() -> cpu_id %d, irq_num %d\r\n", cpu_id, irq_num);
  rt_hw_interrupt_set_target_cpus(irq_num, cpu_id);
  rt_hw_interrupt_set_priority(irq_num, ctrl->config.irq_priority); /* setup interrupt */
@@ -78,10 +77,9 @@ static void FGpioOpsSetupCtrlIRQ(FGpio *ctrl)
 /* setup gpio pin interrupt */
 static void FGpioOpsSetupPinIRQ(FGpio *ctrl, FGpioPin *const pin, FGpioOpsPinConfig *config)
 {
- u32 cpu_id;
+ rt_uint32_t cpu_id = rt_hw_cpu_id();
  u32 irq_num = ctrl->config.irq_num[pin->index.pin];
 
- GetCpuId(&cpu_id);
  LOG_D("in FGpioOpsSetupPinIRQ() -> cpu_id %d, irq_num %d", cpu_id, irq_num);
  rt_hw_interrupt_set_target_cpus(irq_num, cpu_id);
  rt_hw_interrupt_set_priority(irq_num, ctrl->config.irq_priority); /* setup interrupt */