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IIC-OSIC-TOOLS Public
Forked from iic-jku/IIC-OSIC-TOOLSIIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
Python Apache License 2.0 UpdatedAug 21, 2024 -
ChampSim-Branch-Predictor-simulator Public
Forked from ChampSim/ChampSimChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.
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training-fine-tuning-large-language-models-workshop-dhs2024 Public
Forked from dipanjanS/training-fine-tuning-large-language-models-workshop-dhs2024This repository will contain all the presentations, content, hands-on notebooks for a full day Generative AI workshop on Training, Fine-tuning Large Language Models for the DataHack Summit 2024 con…
Jupyter Notebook GNU General Public License v3.0 UpdatedAug 16, 2024 -
OpenROAD-flow-scripts Public
Forked from The-OpenROAD-Project/OpenROAD-flow-scriptsOpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Verilog Other UpdatedAug 16, 2024 -
cocotb Public
Forked from cocotb/cocotbcocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Python BSD 3-Clause "New" or "Revised" License UpdatedAug 15, 2024 -
OpenLane Public
Forked from The-OpenROAD-Project/OpenLaneOpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Python Apache License 2.0 UpdatedAug 15, 2024 -
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priyanshu.github.io Public
Personal website
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Hazard3 Public
Forked from Wren6991/Hazard33-stage RV32IMACZb* processor with debug
Verilog Apache License 2.0 UpdatedAug 9, 2024 -
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buddy-mlir Public
Forked from buddy-compiler/buddy-mlirAn MLIR-based compiler framework bridges DSLs (domain-specific languages) to DSAs (domain-specific architectures).
C++ Apache License 2.0 UpdatedAug 3, 2024 -
UberDDR3 Public
Forked from AngeloJacobo/UberDDR3Opensource DDR3 Controller
Verilog GNU General Public License v3.0 UpdatedJul 28, 2024 -
build-your-own-x Public
Forked from codecrafters-io/build-your-own-xMaster programming by recreating your favorite technologies from scratch.
UpdatedJul 28, 2024 -
llama.lisp Public
Forked from chsasank/llama.lispLisp dialect designed for HPC and AI
Common Lisp GNU Lesser General Public License v2.1 UpdatedJul 25, 2024 -
aws-neuron-sdk Public
Forked from aws-neuron/aws-neuron-sdkPowering AWS purpose-built machine learning chips. Blazing fast and cost effective, natively integrated into PyTorch and TensorFlow and integrated with your favorite AWS services
Python Other UpdatedJul 23, 2024 -
mor1kx Public
Forked from openrisc/mor1kxmor1kx - an OpenRISC 1000 processor IP core
Verilog Other UpdatedJul 18, 2024 -
Pytorch-tutorials Public
Forked from pytorch/tutorialsPyTorch tutorials for beginners
Jupyter Notebook BSD 3-Clause "New" or "Revised" License UpdatedJul 17, 2024 -
vlsi_linkedin_index Public
Forked from amradel2020/vlsi_linkedin_indexThis repo provide an index of VLSI content creators and their materials
UpdatedJul 17, 2024 -
riscV-rv32-simulator Public
Forked from wyvernSemi/riscVOpen source ISS and logic RISC-V 32 bit project
C++ GNU General Public License v3.0 UpdatedJul 11, 2024 -
gem5-bootcamp-env Public template
Forked from gem5bootcamp/gem5-bootcamp-envThe gem5 Bootcamp 2022 environment. Archived.
SCSS Creative Commons Attribution 4.0 International UpdatedJul 10, 2024 -
cvw Public
Forked from openhwgroup/cvwCORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…
C Other UpdatedJul 6, 2024 -
core-v-verif Public
Forked from openhwgroup/core-v-verifFunctional verification project for the CORE-V family of RISC-V cores.
Assembly Other UpdatedJul 5, 2024 -
IHP-Open-PDK Public
Forked from IHP-GmbH/IHP-Open-PDK130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
HTML Apache License 2.0 UpdatedJul 4, 2024 -
VexRiscv Public
Forked from SpinalHDL/VexRiscvA FPGA friendly 32 bit RISC-V CPU implementation
Assembly MIT License UpdatedJul 4, 2024 -
pulp_cluster Public
Forked from pulp-platform/pulp_clusterThe multi-core cluster of a PULP system.
SystemVerilog Other UpdatedJul 3, 2024 -
chisel Public
Forked from chipsalliance/chiselChisel: A Modern Hardware Design Language
Scala Apache License 2.0 UpdatedJul 2, 2024 -
example-socs Public
Forked from ChipFlow/example-socsPython BSD 2-Clause "Simplified" License UpdatedJul 2, 2024