Skip to content

PedroHSCavalcante/uvm-phase-jumping

BranchesTags

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

12 Commits
rtl
rtl
 
 
Makefile
Makefile
 
 
README.md
README.md
 
 
agent.sv
agent.sv
 
 
agent_rb.sv
agent_rb.sv
 
 
coverage.sv
coverage.sv
 
 
diagram-ph-jump.png
diagram-ph-jump.png
 
 
driver.sv
driver.sv
 
 
driver_rb.sv
driver_rb.sv
 
 
env.sv
env.sv
 
 
interface_if.sv
interface_if.sv
 
 
interface_rb.sv
interface_rb.sv
 
 
monitor.sv
monitor.sv
 
 
monitor_rb.sv
monitor_rb.sv
 
 
pkg.sv
pkg.sv
 
 
refmod.cpp
refmod.cpp
 
 
refmod.sv
refmod.sv
 
 
scoreboard.sv
scoreboard.sv
 
 
sequence_in.sv
sequence_in.sv
 
 
sequence_rb.sv
sequence_rb.sv
 
 
shm.tcl
shm.tcl
 
 
simple_test.sv
simple_test.sv
 
 
top.sv
top.sv
 
 
transaction_in.sv
transaction_in.sv
 
 
transaction_out.sv
transaction_out.sv
 
 
transaction_rb.sv
transaction_rb.sv
 
 
uvm-phases.png
uvm-phases.png
 
 

Repository files navigation

Reset Testing with Phase Jumps

"Reset testing is a crucial element of functional sign-off for any chip. To perform reset testin in a self-cheking framework, the architectural components of the entire verification environment need to be correctly synchronized to be made aware of the reset condition. When reset is activated, scoreboards, drivers, and monitors need to be tidied up, and the complex stimulus generation needs to be killed gracefully." (HUNTER, 2016)

To exemplify the use of the reset test in a UVM environment, an environment architecture was proposed. See the diagram below.

References

HUNTER,Brian. Advanced UVM. San Bernardino CA, 2016

About

Simple UVM phase jumping

Topics

verification reset systemverilog uvm on-the-fly microelectronics phase-jump

Resources

Readme
Activity

Stars

7 stars

Watchers

3 watching

Forks

4 forks
Report repository

Releases

No releases published

Packages

No packages published

Languages