Digital logic design tool and simulator

GPT4All: Chat with Local LLMs on Any Device

Verilator open-source SystemVerilog simulator and lint system

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

The official git repository for Contiki, the open source OS for the Internet of Things

The OpenRISC 1000 architectural simulator

Spike, a RISC-V ISA Simulator

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at https://gitlab.com/buildroot.org/buildroot/. Do not open i…

OpenEmbedded/Yocto layer for RISC-V Architecture

Qiskit is an open-source SDK for working with quantum computers at the level of extended quantum circuits, operators, and primitives.

Magic VLSI Layout Tool

Project Website: https://inkscape.org - Code Repository: https://gitlab.com/inkscape/inkscape - Draw freely. 🖌

Algorithm to hardware compilation tools (e.g. C to VHDL).

Multi-platform nightly builds of open source digital design and verification tools

VUnit is a unit testing framework for VHDL/SystemVerilog

Official doxygen git repository

Flexible and powerful data analysis / manipulation library for Python, providing labeled data structures similar to R data.frame objects, statistical functions, and much more

Verilog library for ASIC and FPGA designers

SonicBOOM: The Berkeley Out-of-Order Machine

The MyHDL development repository

This is an active mirror of the KiCad development branch, which is hosted at GitLab (updated every time something is pushed). Pull requests on GitHub are not accepted or watched.

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

🌊 Digital timing diagram rendering engine

Open source O-RAN 5G CU/DU solution from Software Radio Systems (SRS) https://docs.srsran.com/projects/project

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

OpenSCAD - The Programmers Solid 3D CAD Modeller

VHDL synthesis (based on ghdl)

SCR1 is a high-quality open-source RISC-V MCU core in Verilog