Francisco Javier Reina Campo PacoReinaCampo

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I am an Electronic Engineer specialized in digital design and verification, with emphasis on Hardware Description Languages ((System)Verilog, VHDL).

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I am the author of the UVM Primer and the Aerospace & Defense Solutions Manager at Siemens EDA DVT division.

Siemens EDA Boston, MA

UC San Diego La Jolla, CA

VHDL Verification Specialist, OSVVM author, VHDL Trainer (including on OSVVM), IEEE VHDL WG Chair, Yoga Teacher

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