Product Based RISC-V Skilling Program from VSD Corp and Chipcron.

Week-1: Understanding how a C program is compiled using various compilers with the help of the Godbolt platform.

Week-2: Introduction to RISC-V ISA Exploring the RISC-V ISA architecture.Understanding how microarchitecture is defined based on assembly instructions of a program and measuring CPU performance.

Week-3 Selecting an application, write a C code demonstrating its functionality, and subsequently include inline assembly code within the same file to access hardware resources.

Week-4 Generating the Optimised RTL logic specific to the C program and testbench using ChipCron tool. GPIO configuration and functional simulation using UART.

Week-5 GLS Simulation and synthesis of the generated RTL. Synthesis is performed using the yosys tool and simulation using iverilog. Bypassing UART.

Physical Design of the processor.v core using OpenLane is the next step in the design flow.

Acknowledgement

• Kunal Ghosh, VSD Corp.Pvt.Ltd.
• Mayank Kabra, Chipcron Pvt.Ltd.

References

• https://github.com/riscv-collab/riscv-gnu-toolchain

• https://github.com/Rachana-Kaparthi/Sound-based-smart-switch

• https://www.vsdiat.com

• https://github.com/riscv-software-src/riscv-isa-sim