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Pull requests: OpenXiangShan/XiangShan
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debugModule: fix bug,singleStep don't generate exception correctly.
#3266
opened Jul 22, 2024 by
wissygh
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bpu: optimize the clock gate efficiency of bpu/predictors_update_* and bpu/previous_*
#3265
opened Jul 22, 2024 by
Lawrence-ID
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PcTargetMem: Fixed a bug that caused the backend to read the incorrect newest target
#3264
opened Jul 22, 2024 by
TheKiteRunner24
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Backend: pipe fromTop's clintTime and msiInfo for fix timing
#3262
opened Jul 22, 2024 by
xiaofeibao-xjtu
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VLSU: Modify the width of Veew when decode and remove some useless api
#3258
opened Jul 21, 2024 by
Anzooooo
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rv64v: exception check for vector widening reduction instructions
#3243
opened Jul 19, 2024 by
Ziyue-Zhang
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MemBlock: fix timing of scala load/store issue and writeback
timing
Fix bad timing
#3208
opened Jul 16, 2024 by
weidingliu
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Draft
bpu: set ittage not ready when SRAM reset is not done
#3198
opened Jul 14, 2024 by
eastonman
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Backend: modify decode unit to quicken csrr instructions, with other small modification
#3187
opened Jul 11, 2024 by
Squareless-XD
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LSQ: optimize static clock gating coverage and fix x_value in vcs
#3176
opened Jul 10, 2024 by
jin120811
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