RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

System Verilog code describing a fully combinational binarized neural network.

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

Implementation of CNN using Verilog

A convolutional neural network implemented in hardware (verilog)

Educational materials for RISC-V

Verilog Design for a good 16-bit RISC Processor using the LC-3B ISA

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.