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tvip-axi Public
Forked from taichi-ishitani/tvip-axiAMBA AXI VIP
SystemVerilog Apache License 2.0 UpdatedMay 16, 2024 -
veripy Public
Forked from facebookresearch/veripyVeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation, embedded python, IO spec flow, memory wrapper generation, v…
Python Other UpdatedMar 3, 2024 -
XiangShan Public
Forked from OpenXiangShan/XiangShanOpen-source high-performance RISC-V processor
Scala Other UpdatedFeb 26, 2024 -
systemrdl-compiler Public
Forked from SystemRDL/systemrdl-compilerSystemRDL 2.0 language compiler front-end
Python MIT License UpdatedJan 12, 2024 -
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pyslang Public
Forked from MikePopoloski/pyslangPython bindings for slang, a library for compiling SystemVerilog
Python MIT License UpdatedNov 30, 2023 -
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PyRTL Public
Forked from UCSBarchlab/PyRTLA collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than p…
Python BSD 3-Clause "New" or "Revised" License UpdatedOct 27, 2023 -
myhdl Public
Forked from myhdl/myhdlThe MyHDL development repository
Python GNU Lesser General Public License v2.1 UpdatedOct 19, 2023 -
verilog_parser Public
To look neat, Convert verilog into metadata.
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uvm-python Public
Forked from tpoikela/uvm-pythonUVM 1.2 port to Python
Python Apache License 2.0 UpdatedApr 24, 2023 -
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netlist_parser.py Public
Forked from manasdas17/netlist_parser.pyA Python based netlist parser, including Verilog and SPICE
Python GNU General Public License v2.0 UpdatedJul 24, 2015 -
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sveditor-ref-designs Public
Forked from mballance/sveditor-ref-designsReference designs for use in SVEditor benchmarking
Assembly UpdatedAug 4, 2013
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