synchronized communication interface between App and circuitjs based on websockets (synchronization is achieved using the original/unmodified circuitjs websocket API)

New example:
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The VHDL code (e.g. VIVADO) sets the frequency of the output voltage generated by the application board ("sig-gen" in python app) which drives the input voltage of the transformer (circuitjs).

The output voltage of the transformer (circuitjs) is then read by the application board ("ADC" in python app) and input to the VHDL code using 10 digital inputs (VIVADO). The frequency can be changed using the push button B0.

The closed simulation loop runs "in sync" thus making sure that all models are consistent.

Note: simulating in sync with circuitjs is slower than the other options (random, counter, input file), e.g. 1500 Hz i.o. 5000 Hz.

async DIs added to sensitivity list of process in top VHDL module
..

The project now includes connection to circuitjs over websockets to simulate digital inputs.
Also files may be used to simulate digital inputs.
Support of config.ini
Several new features like e.g. highlightning an "open" websocket connection to circuitjs.

bug in calculation of clock period corrected

Files and scripts provided to support generation of an .exe file for Windows.
The generation takes only a few seconds!

01.01.2023
FPGA_HW_SIM_FWK_2
This project is a successor of:
https://github.com/ClarkFieseln/FPGA_HW_SIM_FWK
The main changes are:

• Improved performance:
  • simulation rate increased from max. 330 Hz to up to 40000 Hz!
  • overall stimulus and output simulation increased a factor 120
  • simulation of signals during 4 clock states (raising edge, high, falling edge, low)
  • fix scheduler synchronized with VHDL Simulation Tool over two named pipes, one for sending and one for receiving signal changes serially
    (no longer big amount of "parallel" shared files or pipes are used, which proved to be slow and difficult to synchronize beyond 100Hz)
  • the pipes are of type BYTE or MESSAGE and every WriteFile in the App finishes with "\r\n" which is read with readline() in VHDL
  • std_logic and std_logic_vector transmitted as strings
  • TURBO mode avoids delays between cycles
  • possibility to set/clear "asynchronous" signal changes also "between" clock falling and raising edges, both in sending and receiving directions
  • no use of Event.wait() or oclock.wait() with 10ms delay - use time.sleep() instead
  • no appending to strings in each period, this caused a huge performance penalty!
• Use pygubu (GUI builder for Tkinter) i.o. PyQt for many reasons, but mainly for long-term compatibility, support, and easy installation
  To install just type:
  pip install pygubu
  pip install pygubu-designer
• Simplified and improved code:
  • removed config.ini, log in .csv file, sound effects, temperature example with ADC over SPI
  • easier examples:
    • BTN or SW -> LEDs (left)
    • BTN and SW -> LEDs (right)
    • DIs -> DOs
      (DIs may be a counter or a random number, the upper half of DIs are asynchronous)
• Code with PEP Style Guide
• To install libraries for support of pipes in Windows type:
  pip install pywin32
• TODOs:
  • improve performance by using Cython (?)
  • config.ini, requirements.txt, pyinstaller, ...
  • encapsulated format for pipe data (=id:data,), objects shall not process data depending on it as it is more difficult to extend and maintain
  • use regex to process pipe data (=id:data,)